This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 Custom board hardware design – USB2.0 interface

Other Parts Discussed in Thread: AM62A3, AM62A7-Q1, AM62A3-Q1, AM62A7, AM620-Q1, AM625, AM623, AM625-Q1, AM625SIP

Hi TI Experts,

I have the below queries regarding implementation of USB interface

1. Supported USB interface configuration

2. Is VBUS connection required for Host configuration or Device configuration

3.  Can i have the VBUS supply input connected when the SoC power supply is switched off

4. Is there a power sequencing requirement for VBUS 

5. Can i connect 5V input from the USB connector directly to VBUS 

6. Recommended VBUS supply voltage divider 

7. SOC VBUS input voltage range and Zener diode connection 

8. Supported USB Backup bootmode configuration. 

9. Recommended USB RCALIB resistor 

10. How to deal with the USB unused pins 

11. Need details on the USBx_ID functionality 

12. Power supply switching and protection when the SOC is configured as USB Host

13. Are these recommendations valid for other Sitara processors? 

14. Do you have some recommendations on the Type-C implementation

15. Can i use 3.4K instead of 3.5K.

16. Do the differential signal pins (oLDI, USB, etc.) have the capabilities to adjust the swing of the voltage?

Let me know your thoughts.

  • Hi Board designers, 

    1. Supported USB interface configuration. 

    USB0 and USB1 interfaces support Host or Device or Dual Role (DRD)

    2. Is the VBUS connection required for Host configuration or Device configuration.

    VBUS connection for Host interface is optional. It is recommended to connect the VBUS when the USB interface is configured as Device.

    The recommended voltage range is the divided voltage equivalent of 4.75 V - 5.25 V for normal operation.  

    3. Can i have the VBUS supply input connected when the SoC power supply is switched off

    VBUS IOs are fail-safe. The VBUS input does not have any dependency on the SOC power supply.

    4. Is there a power sequencing requirement for VBUS input 

    USB VBUS IOs are fail-safe and do not have any sequencing requirements.

    5. Can i connect 5 V input from the USB connector directly to VBUS input. 

    VBUS pins cannot be connected directly to external/connector VBUS, as IO are not 5 V compliant.  Recommend using voltage divider and/or current limiter to ensure IO requirements are met.  VBUS pins can be consider fail-safe only if recommended external divider circuit is used. 

    Connection of 3.3 V directly to VBUS input is not allowed or recommended.

    For USB Device interface, it is recommended to connect a switched external USB VBUS supply to the USBx_VBUS input of the SOC through recommended resistor divider.

    6. Recommended VBUS supply voltage divider 

    Refer 9.2.3 USB VBUS Design Guidelines of the device data sheet. Note the use of 1% tolerance resistors.

    7. SOC VBUS input voltage range and Zener diode connection 

    We do not define VBUS thresholds. VBUS thresholds are defined in the USB specification. The thresholds were designed to be compliant to the USB specifications and validated via USB-IF compliance tests.
    The VBUS input has an ESD clamp to the 3.3 V rail. The USB VBUS Design Guidelines section of the datasheet defines the VBUS connection topology. This voltage divider / clamp circuit allows VBUS to go up to 30 V without harming the VBUS input. The Zener diode could be removed and a 20 kohm resistor could be substituted for the 16.5 kohm and 3.5 kohm resistors if your system will never apply a VBUS potential greater than 5.5 V and the 5.5 V is sourced on-board.

    8. Supported USB Backup bootmode configuration. 

    USB0 interfaced is recommended to be configured as a device. USB DFU backup mode works with 0.75V SOC core supply.

    9. Recommended USB RCALIB resistor 

    Refer below section of the Data Sheet 

    6.3.26 USB, 6.3.26.1 MAIN Domain, Table 6-72. USB0 Signal Descriptions

    RCALIB resistor should not exceed 1% at any operating condition for the lifetime of the product.

    10. How to deal with the USB unused pins 

    Refer 6.4 Pin Connectivity Requirements, Table 6-74. Connectivity Requirements

    11. Need details on the USBx_ID functionality  

    There is no dedicated pin for USBx_ID pinned out. This can be implemented using any of the SOC IOs. 

    12. Power supply switching and protection when the SOC is configured as USB Host

    USBx_DRVVBUS can be used to control the power (load) switch. The USB interface or the Linux driver is not checking the status of VBUS to determine if there is a fault condition. In that case, you should connect the fault output of the VBUS power (load) switch to a GPIO and configure the GPIO to generate an interrupt that indicates there has been an over-current condition.

    13. Are these recommendations valid for other Sitara processors? 

    The recommendations are valid for the following family of devices.:

    AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

    14. Do you have some recommendations on the Type-C implementation.

    Refer below starter kit for implementation.

    https://www.ti.com/tool/SK-AM62B-P1

    15. Can i use 3.4K instead of 3.5K.

    it should be Ok to use a 3.4K for the divider. It is recommended to select 3.48K value  based on the availability.

    16. Do the differential signal pins (oLDI, USB, etc.) have the capabilities to adjust the swing of the voltage?

    No.

    Note: 

    Ensure the recommended capacitors are provided for the VBUS supply near to the connector (Host > 120 uF and Device (1-10 uF))

    USBx_DRVVBUS has an internal pulldown enabled by default.


    Refer below documents during the USB interface design.

    Hardware Design Guide for AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 Family of Processors

    https://www.ti.com/lit/pdf/sprad05

    Hardware Design Guide for AM62A7/AM62A3 Devices

    https://www.ti.com/lit/an/sprad85/sprad85.pdf

    AM625 / AM623 / AM625SIP / AM625-Q1 / AM620-Q1 / AM62A7 / AM62A3 Schematic Design and Review Checklist

    https://www.ti.com/lit/an/sprad21b/sprad21b.pdf

    Regards,

    Sreenivasa