TDA4VM: Routing GPIO1_11 interrupt on MCU3_0.

seongmin kim

Prodigy 80 points

Part Number: TDA4VM

HI.

I'd like to use gpio1_11 as input IO in Vision_apps on mcu3_0.

And I want to detect the falling edge of gpio1_11 using interrupt routing.

I have referenced some e2e. and I implemented the code below.

void test_gpio_handler()
{
    cnt++;
    GPIO_clearInt(0);
}

static void SetRmIrqGPIO()
{
    struct tisci_msg_rm_irq_set_req rmIrqReq;
    struct tisci_msg_rm_irq_set_resp rmIrqResp;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params = 0U;
    rmIrqReq.global_event = 0U;
    rmIrqReq.src_id = 0U;
    rmIrqReq.src_index = 0U;
    rmIrqReq.dst_id = 0U;
    rmIrqReq.dst_host_irq = 0U;
    rmIrqReq.ia_id = 0U;
    rmIrqReq.vint = 0U;
    rmIrqReq.vint_status_bit_index = 0U;
    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

   
    rmIrqReq.src_id = TISCI_DEV_GPIOMUX_INTRTR0;
    rmIrqReq.src_index = 11; //Need to add 128 for GPIO1

    /* Set the destination based on the core */
    rmIrqReq.dst_id = TISCI_DEV_GPIOMUX_INTRTR0;  //TISCI_DEV_R5FSS1_CORE0;
    rmIrqReq.dst_host_irq = 16;    //don't know how to set this

    /* Set the destination interrupt */
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

    Sciclient_rmIrqSet(
                (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                &rmIrqResp,
                SCICLIENT_SERVICE_WAIT_FOREVER);
    
}

static void GPIO_configIntRouter(uint32_t portNum, uint32_t pinNum, uint32_t gpioIntRtrOutIntNum, GPIO_v0_HwAttrs *cfg)
{
    GPIO_IntCfg       *intCfg;
    uint32_t           bankNum = 0U;

    intCfg = cfg->intCfg;

    cfg->baseAddr = 0x601000UL;

    bankNum = pinNum/16; /* Each GPIO bank has 16 pins */    

    intCfg[pinNum].intNum = 176 + bankNum;  //CSLR_R5FSS1_CORE0_INTR_GPIOMUX_INTRTR0_OUTP_16
    intCfg[pinNum].intcMuxNum = INVALID_INTC_MUX_NUM;
    intCfg[pinNum].intcMuxInEvent = 0;
    intCfg[pinNum].intcMuxOutEvent = 0;
}

void gpio_ecap_init(void)
{
    GPIO_v0_HwAttrs gpio_cfg;
    
    Board_moduleClockEnable(TISCI_DEV_GPIO1);
    
    GPIO_socGetInitCfg(0, &gpio_cfg);   //
    gpio_cfg.baseAddr = 0x601000UL;
    
    GPIO_configIntRouter(1, 11, 0, &gpio_cfg);
    
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG140, 0x0050007);
    
    GPIO_socSetInitCfg(0, &gpio_cfg);

    GPIO_setCallback(0, test_gpio_handler);

    GPIO_init();
    SetRmIrqGPIO();
    
    GPIO_setCallback(0, test_gpio_handler);

    GPIO_enableInt(0);
    GPIO_clearInt(0);
}

After gpio setting, I confirmed that the GPIO read value was changing.

But the gpio interrupt handler doesn't work.

Is dst_host_irq correct?

how to work the gpio handler?

over 2 years ago

0 Brijesh Jadav over 2 years ago

TI__Guru**** 484655 points

Hi,

As per the below entry in the rm-cfg.c file, yes, dst_host_irq value of 16 seems to be correct. It is assigned to mcu3_0 in the rm-cfg.c file.

{
.start_resource = 16,
.num_resource = 4,
.type = RESASG_UTYPE (J721E_DEV_GPIOMUX_INTRTR0,
RESASG_SUBTYPE_IR_OUTPUT),
.host_id = HOST_ID_MAIN_1_R5_0,
},

can you please check the return value of Sciclient_rmIrqSet API and confirm that it is returning success?

Also can you check if bit is set in GPIO_INT_STAT register? If the bit is not set here, GPIO is not generating interrupt.. We would need to then first solve this issue.

Regards,

Brijesh

0 seongmin kim over 2 years ago in reply to Brijesh Jadav

Prodigy 80 points

Hi,

Thanks for your reply.

After clearing the GPIO interrupt with GPIO_INT_STAT 1, we confirmed that the GPIO_iNT_STAT read value changes.

But, return value of Sciclient_rmIrqSet wasn't 0. the result was fail. I miss this.

What causes this problem?

0 Brijesh Jadav over 2 years ago in reply to seongmin kim

TI__Guru**** 484655 points

ok, if this is returning error, interrupt is not really routed correctly. I see you are using same src_id and dst_id, but since you want to connect gpio to irq, please src_id as GPIO ID and dst_id as R5F Host, like below.

rmIrqReq.src_id = TISCI_DEV_GPIO1;
rmIrqReq.src_index = 0; // This is Bank ID, sciclient API supports Bank interrupt only.

/* Set the destination based on the core */
rmIrqReq.dst_id = TISCI_DEV_R5FSS1_CORE0;
rmIrqReq.dst_host_irq = 176; //this is host IRQ number

Regards,

Brijesh

0 seongmin kim over 2 years ago in reply to Brijesh Jadav

Prodigy 80 points

I edited the code according to your answer. And the result was a pass.

But, The handler still doesn't work.

0 Brijesh Jadav over 2 years ago in reply to seongmin kim

TI__Guru**** 484655 points

ok, do you see GPIO_INT_STAT register being set? Also is the Bank Interrupt enabled in the GPIO module?

0 seongmin kim over 2 years ago in reply to Brijesh Jadav

Prodigy 80 points

yes.

the '0' bank interrupt(GPIO_BINTEN) is enabled.

the GPIO_IN_STAT of GPIO1_11 is seted.

Check using qnx cmd

// check the GPIO_INSTAT
# in32 0x00601034    
0x00601034 : 0x00000800

// Clear the GPIO_INSTAT
# out32 0x00601034 0x00000800
# in32 0x00601034             
0x00601034 : 0x00000000

// after signal input

# in32 0x00601034          
0x00601034 : 0x00000800

// check bank interrupt enable
# in32 0x00601008 
0x00601008 : 0x00000001

+1 seongmin kim over 2 years ago

Prodigy 80 points

I confirmed that the gpio handler is waking up.

I replaced GPIO_setCallback with Osal_RegisterInterrupt.

void test_gpio_handler()
{
    cnt++;
    GPIO_clearInt(0);
}

void AppGpioCallbackFxn(uintptr_t arg)
{
    cnt++;
    GPIO_clearInt(0);
}

void reg_func(int intNum)
{
    OsalRegisterIntrParams_t    intrPrms;
    HwiP_Handle hwiHandle;
    OsalInterruptRetCode_e      osalRetVal;

    Osal_RegisterInterrupt_initParams(&intrPrms);
    intrPrms.corepacConfig.arg          = (uintptr_t)NULL;
    intrPrms.corepacConfig.isrRoutine   = &AppGpioCallbackFxn;
    intrPrms.corepacConfig.priority     = 1U;
    intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
    intrPrms.corepacConfig.intVecNum        = intNum;

    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    appLogPrintf("[%s:%d] Osal_RegisterInterrupt osalRetVal=%d\n",__func__, __LINE__,osalRetVal);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
         appLogPrintf ("Osal_RegisterInterrupt fail \n");
    }else{
         appLogPrintf ("Osal_RegisterInterrupt fine \n");
    }
}

static void SetRmIrqGPIO()
{
    struct tisci_msg_rm_irq_set_req rmIrqReq;
    struct tisci_msg_rm_irq_set_resp rmIrqResp;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params = 0U;
    rmIrqReq.global_event = 0U;
    rmIrqReq.src_id = 0U;
    rmIrqReq.src_index = 0U;
    rmIrqReq.dst_id = 0U;
    rmIrqReq.dst_host_irq = 0U;
    rmIrqReq.ia_id = 0U;
    rmIrqReq.vint = 0U;
    rmIrqReq.vint_status_bit_index = 0U;
    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

   
    rmIrqReq.src_id = TISCI_DEV_GPIO1;
    rmIrqReq.src_index = 0; //Need to add 128 for GPIO1

    /* Set the destination based on the core */
    rmIrqReq.dst_id = TISCI_DEV_R5FSS1_CORE0;
    rmIrqReq.dst_host_irq = 176;    //don't know how to set this

    /* Set the destination interrupt */
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

    Sciclient_rmIrqSet(
                (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                &rmIrqResp,
                SCICLIENT_SERVICE_WAIT_FOREVER);
    
}

static void GPIO_configIntRouter(uint32_t portNum, uint32_t pinNum, uint32_t gpioIntRtrOutIntNum, GPIO_v0_HwAttrs *cfg)
{
    GPIO_IntCfg       *intCfg;
    uint32_t           bankNum = 0U;

    intCfg = cfg->intCfg;

    cfg->baseAddr = 0x601000UL;

    bankNum = pinNum/16; /* Each GPIO bank has 16 pins */    

    intCfg[pinNum].intNum = 176 + bankNum;  //CSLR_R5FSS1_CORE0_INTR_GPIOMUX_INTRTR0_OUTP_16
    intCfg[pinNum].intcMuxNum = INVALID_INTC_MUX_NUM;
    intCfg[pinNum].intcMuxInEvent = 0;
    intCfg[pinNum].intcMuxOutEvent = 0;
}

void gpio_ecap_init(void)
{
    GPIO_v0_HwAttrs gpio_cfg;
    
    Board_moduleClockEnable(TISCI_DEV_GPIO1);
    
    GPIO_socGetInitCfg(1, &gpio_cfg);   //
    gpio_cfg.baseAddr = 0x601000UL;
    
    GPIO_configIntRouter(1, 11, 0, &gpio_cfg);
    
    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG140, 0x0050007);
    
    GPIO_socSetInitCfg(1, &gpio_cfg);

    GPIO_setCallback(0, test_gpio_handler);

    GPIO_init();
    //SetRmIrqGPIO();
    ref_fun(176);
    
    GPIO_setCallback(0, test_gpio_handler);

    GPIO_enableInt(0);
    GPIO_clearInt(0);
}

but, Why doesn't GPIO setCallback work?

0 Brijesh Jadav over 2 years ago in reply to seongmin kim

TI__Guru**** 484655 points

No sure exactly, but could be driver limitation. It might not be calling the callback.. Need to check in the driver.

But i think since you have now callback working, nothing else is required, correct? In that case, please close this ticket.

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TDA4VM: Routing GPIO1_11 interrupt on MCU3_0.