Hi,
I am a newbie to the VC5505 DSP. I have the following questions regarding the setup of the SPI.
Question 1: I was trying to understand the snippet of code used to set the value of CLKDV in csl_spi.c, which is as follows,
/* Clock division must be gater or equal to 2 */
if (spiHwConfig->spiClkDiv > 2)
{ sysClkDiv = spiHwConfig->spiClkDiv - 1; }
else
{ sysClkDiv = 2;
/* Default clock division is 2 */
}
/* Set Clock division */
CSL_FINS(CSL_SPI_REGS->SPICDR, SPI_SPICDR_CLKDV, sysClkDiv);
However, in the SPI user's guide it says that the CLKDV must greater than or equal to 3. Doesn't this contradict the code. What am I missing?
Question 2: How can I set the sysClk to 120 MHz for the VC5505? Can this be done by using the 8508.c5505evm_pg20.gel file and setting the PLL to 120 MHz.
Thanks for the help.
Ajay.
