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AM6422: AM64x OSPI connect with 2 QSPI device

Part Number: AM6422
Other Parts Discussed in Thread: AM62A3, AM625, AM623, AM62A7

Hi Team

Customer is studying one possible OSPI connection method, which is connecting with QSPI Flash and QSPI FPGA separately with different device selection .

Is this an available solution form practice perspective? The ospi driver will be developed in their own RTOS  running on A53.

According to below 2 tickets, the configuration/initialization software should be a gap. 

Could you share your suggestion on this solution?

(1) AM2431: OSPI and QSPI running with two devices on the same bus - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

AM2431: OSPI interface using multiple Chip selects is not supported with Sysconfig - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

-Thomas

  • Thomas,

    I can't comment on RTOS SW but please see below note in the AM62x Schematic Checklist for general feasibility, the same will apply to AM64x as well (this is being updated).

    https://www.ti.com/lit/pdf/sprad21

    AM625/AM623 and AM62A7/AM62A3 Schematic Design and Review Checklist

    Depending on your system the best might be to use two different/dedicated SPI modules (OSPI for the fast memory, and one of the McSPI I/F for the slower/less critical one).

    Regards, Andreas

  • Andreas,

    As OSPI support four device chip-select, so it should support multiple device connection, considering the signal integrity reason in high speed, the guide recommends used as point to point data bus. 

    To make the suggestion more accurately,  may I ask how much clock to be thought as "high speed"?

    N_SS_OUT0 O External SPI device chip-select 0

    N_SS_OUT1 O External SPI device chip-select 1

    N_SS_OUT2 O External SPI device chip-select 2

    N_SS_OUT3 O External SPI device chip-select 3

    -Thomas

  • As OSPI support four device chip-select, so it should support multiple device connection, considering the signal integrity reason in high speed, the guide recommends used as point to point data bus. 

    I was told by the HW experts the main concern is around the clocks. You cannot ensure proper clock signaling with multiple devices connected, as the OSPI IP is not designed for this.

    To make the suggestion more accurately,  may I ask how much clock to be thought as "high speed"?

    Even at relatively "low" speed like 10MHz it was said proper behavior may not be achievable. We don't have any characterization/data for the same. Hence my recommendation to use different interfaces.

    Regards, Andreas