TMS320C6748: TMS320C6748: Reset function

The problem is as follows:
  The program has been burned into 6748 and extended to EMIFA's 8bit NAND. In the cmd file, some of the code is defined in L2 space and some is defined in the 16bit SDRAM of EMIFA extension. If it is powered on and reset, the program can successfully load every time and all functions are running normally. But our product has designed an external reset circuit, which connects the reset signal to the RST signal of 6748. If the signal is output at a low level, there is a 50% probability that 6748 cannot successfully reset the load. The boot configuration pins have been checked for any design errors.
  In addition, our 6747 product is also designed in the same way: it uses the same reset circuit design, and the 6747 system uses the same NAND and SDRAM. Our 6747 product has never encountered this problem before

  The reset circuit is as follows：

Additionally, I would like to add that when a reset is triggered on the HMI product, the final output signal (/RST) waveform to the 6748-RST pin is as follows:

As shown above, the decrease time of the/RST signal is approximately 400us, and the low-level duration is about 300ms. This waveform has been triggered multiple times on our HMI product. Sometimes 6748 can be loaded, sometimes it cannot be loaded (but as long as the system is powered on and reset, 6748 can be successfully loaded)

Hello Cayden

Thank you for the query.

The slow slew rate could be one of the probable issue.

Can you please remove C174, C184 and C182 and perform a test.

Regards,

Sreenivasa

Attempted to remove capacitors C174, C184, and C182, and the RST signal decrease time became 3-20us, but the phenomenon still did not improve. The reset was sometimes successful, and sometimes failed. After checking the situation of each reset failure, the falling edge of the/RST signal is also 3-20us, and the time is random. It does not mean that a long falling time is the reason for the reset failure

Hello Cayden

Thank you for the inputs.

• Reset output available in active-low (TPS3820, TPS3823, TPS3824, and TPS3825), active-high (TPS3824 and TPS3825), and open drain (TPS3828)

I assume you are using the device shown in the schematics.

You will have to root cause why the /RST rise time is 20uS.

Is the /RST directly connected to the DSP.

Regards,

Sreenivasa

Hello Cayden

Have you been able to do some additional tests and make progress?

Regards,

Sreenivasa

From the source to the reset pin of the DSP, there is no capacitive load on the entire reset signal channel. The reset chip used is TPS3823-33DBVR, as shown in the previous circuit diagram. The/RST signal is directly connected to the reset pin of the DSP (6748-K14 pin). When the test/RST signal jumps from high to low, the descent time is 3-20us. Whether it is 3us or 20us, there is a probability of failure during reset. At present, we no longer have a good rectification or testing plan

Hello Cayden

Thank you.

Can you please confirm if the reset phenomenon that you described is being performed when the board is running?

If you switch off and switch on the board, can you confirm if the reset works consistently.

Regards,

Sreenivasa

Yes, the board is running our final product program, and all functions are normal. When a button is pressed on the HMI, the HMI will drive the (MAIN-RS) signal shown in the circuit above to a low level for a duration of 300ms, and then pull it up again. At this point, there is a high probability that the DSP will be unable to load the program
As long as the DSP is turned on and powered on again, it can successfully load the program and operate normally. After multiple starts and restarts, there is no problem

Hello Cayden

Thank you.

If i am understanding correctly the board has not issues when powered up or during repeated power-ups.

The issue seen is with the manual reset.

Have you removed the cap at the output of and gate.

Can you please measure the AND gate output timing?

Regards,

Sreenivasa