EVM6670L AMC compatible carrier board, AIF2 timer pins design problem

Hi,

Can I see your schematic for TMDXEVM6670L?

you need at least PHYSYNC and RADSYNC signal and it requires DSP timer0 output signal if the board has dual DSP on it.

if it is single DSP version, you don't need to care about all input pins you described.

Regards,

Albert

Hi, Albert

Thank you very much for your timely reply!              the schematic for TMDXEVM6670L is as follows:

(I am sorry I have tried many times to upload the whole schematic, but all failed, i think maybe it's too big ,so I have picked up some pages which have some connections with AIF2)

8787.TMS320C6670_EVM.pdf

2352.TMS320C6670_EVM2.pdf

2553.TMS320C6670_EVM3.pdf

1、There is only one DSP on the EVM, what do you mean by saying that

 "if it is single DSP version, you don't need to care about all input pins you described " ?

If so, how do the AIF2 timer begin trigger events? I am reallly confused.

2、For the purpose of  connecting 2 TMDXEVM6670L for more tests, now we are designing the conversion board,  I want to know that how can we give the signals (PHYSYNC and RADSYNC ) for dual DSP debug?   DSP timer0 output signal ? but they are from indepent boards. Do we need more considerations?

Waiting for your help! thanks very much.

Tao

Tao,

I requested schematic because I wanted to confirm that you are not using new EVM design.

there are some differences between new EVM and the current one that you are using.

For dual DSP operation, you should get new EVM which will be released Oct. this year. we may talk more about that when you get the board.

for current EVM, you don't need to use external sync pin or RP01 input.

you just can change the AT Rad and Phy timer sync option to SW debug sync option. (please see our example code in CSL)

For dual DSP EVM, we need external sync pulse for both DSPs and Timer 0 output of DSP1 will be used for Physync and Radsync input source.

the new EVM connection board will have these switch and jumpers and new clock option for AIF2

Hope this could help to you.

Regards,

Albert

Hi, Albert.

I am very interested in this question, so I read all your word. But I am still very confused about how to deal with the PHYSYNC & RADSYNC signal if I want to connect two EVM together. Should I generate a clock signal from the EVM1 and connect it to the  PHYSYNC or the RADSYNC of EVM2? Thx

odzy

Albert

 I have read the code about AIF2  you provided in the CSL,  for the current EVM, we can use the SW debug option. yes, I am clear now. but for single DSP, it is limited to do more tests.  what test can we do?

Here I have another 2 questions to consult you:

1、Is the design of the new EVM similar to EVM6474? so some high speed interfaces ( Hyperlink、 SRIO、AIF2) are connected to each other DSP ?

2、Now that we haven't got the new EVM, and it must be a long time for this,  we want to do dual DSP AIF2 communication based on available boards. 

I decide to use the timer0 output of DSP1 itself to trigger PHYSYNC/RADSYNC? but the timer output doesn't connnect to the AMC card,  it has been connected  to a 80-pin extension header. A jump wire can be used to connect the timer output to AMC conversion card to give the  signals of dual DSP.but the dual DSP from dual  EVM has different clock source, do you think it will affect the sync of two AIF2 interface?

If so, can you give some advices to avoid the influence? can we acheive our test ?

thank you !

Regards.

Tao

yes. timer 0 output one time high pulse (it is not clock) can activate Phy and Rad sync for both DSPs.

-Albert