Part Number: AM5729
Hi,
The McASP Design Guide makes reference to Rx FSG in figure 2 that sits between BCLK and FSYNC. However, I cannot seem to find any reference to this in the datasheet, nor any control over the divisor down to FSYNC within the register outline. Just wondering how I can control thr BCLK to FSYNC frequency division factor.
Regards
Jared
