Other Parts Discussed in Thread: TLV320ADC6140, PROCESSOR-SDK-AM57X
Hi,
I am currently trying to interface to an external codec running as a slave with clocks provided by the mcasp. My understanding is that the MCASP AUXCLK can be sourced from either OSC0 or OSC1. Given the fact that I want to achieve an FSYNC that is 44.1kHz my plan is to use OSC1 through SYS_CLK2 running at 22.5792 Mhz. I have attempted to set this up using the following device tree configuration blocks:
compatible = "simple-audio-card";
simple-audio-card,name = "tlv320adc6140";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&mcasp>;
simple-audio-card,frame-master = <&mcasp>;
mcasp: simple-audio-card,cpu {
sound-dai = <&mcasp1>;
clocks = <&mcasp1_ahclkx_mux>;
};
adc: simple-audio-card,codec {
sound-dai = <&tlv320adc6140>;
};
};
&mcasp1 {
compatible = "ti,dra7-mcasp-audio";
assigned-clocks = <&mcasp1_ahclkx_mux>;
assigned-clock-parents = <&sys_clkin2>;
#sound-dai-cells = <0>;
status = "okay";
op-mode = <0>; // I2S Mode
tdm-slots = <2>; // 2 channels active
num-serializer = <16>; // define all 16. Keep inactive ones for completeness and to ensure axr10 and axr11 used
serial-dir = < // 0: INACTIVE, 1: TX, 2: RX - ax10 Tx | ax11 Rx
0 0 0 0
0 0 0 0
0 0 1 2
0 0 0 0
>;
tx-num-evt = <1>;
rx-num-evt = <1>;
};
I have also hacked into the driver clk_id = 1 in the davinci_mcasp_set_sysclk function to ensure auxclk is used as the source ( where can I set this within the device tree to avoid this hack?)
However, it seems as though the clock source is not being set correctly as my output frequencies as measured on a scope are not correct. Within the driver I am printing the sysclk and blck frequency which are as follows for the command:
arecord -D hw:1,0 -c2 -f S32_LE -r 44100 test.wav
[ 89.888155] mcasp: Running with slots : 2 | rate : 44100 | sbits : 32
[ 89.888182] mcasp: sysclk freq = 22579200
[ 89.888204] mcasp: bclk freq = 2822400
However, the output bclk frequency does not match that indicated by the driver and sits at 2.5Mhz. Since the division factor is 8 it suggests that the AUXCLK is actually running at 20Mhz which is what OSC1 is running at clearly indicating I am not changing the AUXCLK source correctly. have verified through /sys/kernel/debug/clk/clk_summary that the clock is in fact running at 22.5729 Mhz as shown below:
sys_clkin2 0 1 22579200 0 0
mcasp1_ahclkx_mux 0 1 22579200 0 0
sys_clk2_dclk_div 0 0 22579200 0 0
Here is my MCASP register values:
|--------------------------------------------|
| Reg. Name | Reg. Addr | Reg. Val. |
|--------------------------------------------|
| MCASP_PID | 0x48460000 | 0x44307B03 |
| PWRIDLESYSCONFIG | 0x48460004 | 0x00000002 |
| MCASP_PFUNC | 0x48460010 | 0x00000000 |
| MCASP_PDIR | 0x48460014 | 0xB4000400 |
| MCASP_PDOUT | 0x48460018 | 0x00000000 |
| MCASP_PDIN | 0x4846001C | 0x1C000800 |
| MCASP_PDCLR | 0x48460020 | 0x00000000 |
| MCASP_GBLCTL | 0x48460044 | 0x0000001F |
| MCASP_AMUTE | 0x48460048 | 0x00000000 |
| MCASP_LBCTL | 0x4846004C | 0x00000000 |
| MCASP_TXDITCTL | 0x48460050 | 0x00000000 |
| MCASP_GBLCTLR | 0x48460060 | 0x0000001F |
| MCASP_RXMASK | 0x48460064 | 0xFFFFFFFF |
| MCASP_RXFMT | 0x48460068 | 0x000180F0 |
| MCASP_RXFMCTL | 0x4846006C | 0x00000113 |
| MCASP_ACLKRCTL | 0x48460070 | 0x000000A7 |
| MCASP_AHCLKRCTL | 0x48460074 | 0x00008000 |
| MCASP_RXTDM | 0x48460078 | 0x00000003 |
| MCASP_EVTCTLR | 0x4846007C | 0x00000001 |
| MCASP_RXSTAT | 0x48460080 | 0x0000015C |
| MCASP_RXTDMSLOT | 0x48460084 | 0x00000001 |
| MCASP_RXCLKCHK | 0x48460088 | 0x4C000000 |
| MCASP_REVTCTL | 0x4846008C | 0x00000000 |
| MCASP_GBLCTLX | 0x484600A0 | 0x0000001F |
| MCASP_TXMASK | 0x484600A4 | 0xFFFFFFFF |
| MCASP_TXFMT | 0x484600A8 | 0x000100F0 |
| MCASP_TXFMCTL | 0x484600AC | 0x00000013 |
| MCASP_ACLKXCTL | 0x484600B0 | 0x001800E7 |
| MCASP_AHCLKXCTL | 0x484600B4 | 0x00188000 |
| MCASP_TXTDM | 0x484600B8 | 0x00000000 |
| MCASP_EVTCTLX | 0x484600BC | 0x00000000 |
| MCASP_TXSTAT | 0x484600C0 | 0x0000010C |
| MCASP_TXTDMSLOT | 0x484600C4 | 0x0000017F |
| MCASP_TXCLKCHK | 0x484600C8 | 0x00000000 |
| MCASP_XEVTCTL | 0x484600CC | 0x00000000 |
| MCASP_CLKADJEN | 0x484600D0 | 0x00000000 |
| MCASP_XRSRCTL0 | 0x48460180 | 0x00000000 |
| MCASP_XRSRCTL1 | 0x48460184 | 0x00000000 |
| MCASP_XRSRCTL2 | 0x48460188 | 0x00000000 |
| MCASP_XRSRCTL3 | 0x4846018C | 0x00000000 |
| MCASP_XRSRCTL4 | 0x48460190 | 0x00000000 |
| MCASP_XRSRCTL5 | 0x48460194 | 0x00000000 |
| MCASP_XRSRCTL6 | 0x48460198 | 0x00000000 |
| MCASP_XRSRCTL7 | 0x4846019C | 0x00000000 |
| MCASP_XRSRCTL8 | 0x484601A0 | 0x00000000 |
| MCASP_XRSRCTL9 | 0x484601A4 | 0x00000000 |
| MCASP_XRSRCTL10 | 0x484601A8 | 0x00000019 |
| MCASP_XRSRCTL11 | 0x484601AC | 0x00000002 |
| MCASP_XRSRCTL12 | 0x484601B0 | 0x00000000 |
| MCASP_XRSRCTL13 | 0x484601B4 | 0x00000000 |
| MCASP_XRSRCTL14 | 0x484601B8 | 0x00000000 |
| MCASP_XRSRCTL15 | 0x484601BC | 0x00000000 |
| MCASP_WFIFOCTL | 0x48461000 | 0x00001004 |
| MCASP_WFIFOSTS | 0x48461004 | 0x00000000 |
| MCASP_RFIFOCTL | 0x48461008 | 0x00010101 |
| MCASP_RFIFOSTS | 0x4846100C | 0x00000000 |
|--------------------------------------------|
I am just looking for some guidance on how I ensure that the AUXCLK MCASP source is the 22.5729 output of OSC1 and not OSC0 as there clearly is still an error in my device tree setup. I need to rely on internally generated clock source for MCASP and don't have the ability to provide an external source through AHCLKR.
