AM6442: RGMII delay figure understanding

Hello Thierry HAUSER

Thank you for the query.

I will assign to the device expert to support.

For the CPSW3G refer below expert note:

RGMII_ID should be hidden from ctrl mmr as it is not timed, tested, or characterized.

Regards,

Sreenivasa

Hello Sreenivasa,
I would re precise that my question is related to all AM6442 RGMII available interfaces (CPSW3G and PRU).
I ask it with another approach  : does tosu(TD-TXC)/tosu(TX_CTL-TXC)/toh(TXC-TD)/toh(TXC-TX_CTL) timings "embed" all skew of https://www.ti.com/lit/an/snla243/snla243.pdf  (TskewT + IDvar + IOskew) ? if yes, it would answer to my question.
Thanks for your feedback.

B.R.
Thierry

Thanks peaves for your answer, 

Does these timings includes all skews (excepted of course PCB skew) ?

B.R.

Thierry

I'm not sure if I fully understand you question. I already told you datasheet timing parameters define the input requirements and output switching characteristics at the package terminals. What other skews can there be other than PCB skews? 

Regards,
Paul

Hello Paul,
I just would like to know if tosu(TD-TXC) include all skew between Data & Clock for instance, or does any have to be added to min 1.2ns ?

B.R.

Thierry

This parameter is basically saying we provide at least 1.2ns of setup time to the attached RGMII PHY. The value could be larger than 1.2ns, but not smaller than 1.2ns. The RGMII specification requires the attached PHY to operate with as little as 1.0ns of setup time. Therefore, we are providing at least 200ns of margin, minus any trace length mismatch on the customers PCB.

Regards,
Paul