Hi, All,
I use C6713B. My digital board has Xilinx's FPGA Spartan-6 LX25 and TI's DSP C6713B. I use EDMA to transfer data between DSP and FPGA. I am also the engineer who design the glue logic on FPGA side to EDMA data transfer.
I have been tested my FPGA EDMA interface for a while. I have a few block rams and registers inside my FPGA. The data transfer between DSP and rams/registers of FPGA is one way: EDMA write. I have no problem with EDMA write. I also have a FIFO in FPGA which is used as data buffer from ADCs to DSP. That is EDMA read. I have a few problems with EDMA read.
EDMA read is 1-D transfer. The data buffer has 12000 frames and each frame has 3 32-bit words. The total buffer size is 3 X 12000 = 36000 words. The problems are:
(1) The first frame space in DSP data buffer is filled with 0x00000000, 0x00000000, 0x00000000. And the transfered data actually is put from second frame address. The entire data is offset by 1 frame space. That means the first frame data locates at buffer starting address + 3 words.
(2) The last frame data is lost.
(3) The first data word of the second last frame has been corrupted.
I have used ChipScope (a software logic analyzer of Xilinx) check data from FPGA side. I have seen ce_not, ads_not and oe_not showing at proper time, and data on the bus also on the right time, especially during the first frame and last frame. I suspect that my problem is on DSP side.
I use GPIO pins as hand shake signals. gp4/ext-int4 is for EDMA read channel. Below is my partial EDMA configuration code:
EDMA_Handle ConfigureReceiverEDMA( Uint32 *pSource, Uint32 nFrames, Uint32 nElementsInFrame, Uint32 *pDestination) { // configure EDMAINT channel parameter // EDMA interrupt generation setup (see C6000 EDMA Reference Guide p 1-37 edmaReceiverADC.opt = EDMA_OPT_RMK( EDMA_OPT_PRI_HIGH, EDMA_OPT_ESIZE_32BIT, EDMA_OPT_2DS_NO, EDMA_OPT_SUM_NONE, EDMA_OPT_2DD_NO, EDMA_OPT_DUM_INC, EDMA_OPT_TCINT_YES, EDMA_OPT_TCC_OF(EDMA_CHA_EXTINT4), EDMA_OPT_LINK_NO, EDMA_OPT_FS_YES); edmaReceiverADC.src = (Uint32)pSource; edmaReceiverADC.cnt = EDMA_CNT_RMK( EDMA_CNT_FRMCNT_OF(nFrames-1), EDMA_CNT_ELECNT_OF(nElementsInFrame) ); edmaReceiverADC.dst = (Uint32)pDestination; edmaReceiverADC.idx = (Uint32)0; edmaReceiverADC.rld = (Uint32)0; /* Initialize EDMA Handler for data from optical receivers */ // Open EDMA channel FPGA Read Adc hEDMA_FpgaReadAdc = EDMA_open(EDMA_CHA_EXTINT4, // EDMA channel # EDMA_OPEN_RESET); // EDMA channel flag EDMA_config(hEDMA_FpgaReadAdc,&edmaReceiverADC); EDMA_map(IRQ_EVT_EXTINT4, EDMA_CHA_EXTINT4); // Allocate the transfer complete code passed in and returns the same TCC // number if successful, or "-1" otherwise. EDMA_intAlloc(EDMA_CHA_EXTINT4); EDMA_intHook(EDMA_CHA_EXTINT4, (EDMA_IntHandler)HWI_edmaDispatcher); return hEDMA_FpgaReadAdc;
}
void
// GPIO_pinWrite(hGpio, GPIO_PIN7, 1); EDMA_config(hEDMA_FpgaReadAdc,&edmaReceiverADC); EDMA_intEnable(EDMA_CHA_GPINT4); EDMA_enableChannel(hEDMA_FpgaReadAdc); EDMA_setChannel(hEDMA_FpgaReadAdc); GPIO_pinWrite(hGpio, GPIO_PIN7, 0); IRQ_enable(IRQ_EVT_GPINT6); }
I am not sure what causes the problem.
Please help me to diagnize the problem. Thank you!
Lisa
