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SK-AM64B: TPS6522053

Huynh Nguyen
Intellectual 420 points
Part Number: SK-AM64B
Other Parts Discussed in Thread: TMDS64EVM

Hi,

1.How is the characteristics of power down sequence timing with respect to USB power (5V) removal from U77 (LM61460A)

which affects the VCC3V3SYS_EXT supply input to U65 (PMIC TPS6522053) given the current design of SK-AM64B board?

Will the behavior 5V power loss to be the same as TEST_POWERDOWN (TPS6522053_EN) logic input to guarantee the

power OFF sequences of TPS6522053 ?

2. Is it better to use U77-pin5 (PGOOD) to drive TPS6522053_EN of U65 to guarantee the 120us power loss early detection ?

This is not on the current design of SK-AM64B.

Thanks,

Huynh

  • 0
    TI__Guru**** 190059 points

    Hello Huynh

    Thank you for the query.

    I will assign to the PMIC team to answer.

    I will continue to review and provide any additional inputs i may have.

    Regards,

    Sreenivasa

  • 0
    TI__Mastermind 22206 points

    Hi,

    Thanks for reaching out. Please find the responses below and let us know if there are any questions.

    • If the pre-regulator (VCC3V3SYS_EXT) is disconnected from the PMIC supply, it is called an uncontrolled power-down. In this scenario VSYS goes below the UVLO, PMIC is turned OFF, unable to control the power down sequence and all rails turn OFF simultaneously.   

    • If TEST_POWERDOWN (TPS6522053_EN) is pulled low while the the PMIC has a valid supply voltage, it is called a controlled power-down sequence. In this scenario the PMIC executes the power-down sequence that was programmed on the NVM memory. Here is the link to the TPS6522053 Technical Reference Manual (TRM) that shows the default NVM settings. The power-down sequence diagram can be found on page#9. TPS6522053 Technical Reference Manual

    • U77-pin5 (PGOOD) can be use to drive TPS6522053_EN low and trigger the power-down sequence but it needs to allow enough time for the PMIC to complete the power-down sequence before the supply voltage (VSYS) goes below the UVLO threshold. To mitigate this we recommend adding enough capacitance (within the allowed range) to slow down the turn OFF of the pre-regulator (VCC3V3SYS_EXT). 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Intellectual 420 points

    Hello Brenda,

    Thank you for quick response. As I understand the U77-pin5 (PGOOD) can be use to drive TPS6522053_EN to control precisely when the power loss detection occurs before the VCC3V3SYS_EXT is starting to decay. If known system current consumption then the holding capacitance can be calculated to guarantee enough time for SELF controlled power down sequence of about 20ms.

    So the question arises from the uncontrolled power down, is it affecting the safety of CPU in terms of latent failure ?

    Regards,

    Huynh

  • 0 in reply to Huynh Nguyen
    TI__Mastermind 22206 points

    Hi Huynh,

    Sreenivasa from the processor team should be able to comment on how the uncontrolled power down could affect the safety CPU in terms of latent failure. Due to the time zone difference, please allow 24-48Hrs for his response. 

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Guru**** 190059 points

    Hello Huynh,

    Please refer below input i received from the device expert.

    We do not distinguish between controlled vs non-controlled power-down.  We expect the system designer to implement a power solution that never violates our power-down sequence defined in the datasheet.  They may need to characterize their power consumption on the various rails and size capacitors to hold some rails longer than others to provide the proper power-down sequence even when there is a non-controlled power-down event.

     We also do not define what will happen to our device if they violate the power-down sequence because we never expect this to happen.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Intellectual 420 points

    Hello Sreenivasa;

    Thanks for your fair response.

    Is it reasonable and safe to say that TMDS64EVM or SK-AM64B development kit satisfies the power down sequences when the +12V input brick or USB-C (5Vsupply) is removed from respective platform ? These are TI platforms and therefore it must conform to the specifications of related AM64XX power down sequences. I guess the answer is YES ???

    Regards;

    Huynh

  • +1 in reply to Huynh Nguyen
    TI__Guru**** 190059 points

    Hello Huynh,

    Thank you.

    Please read the below note regarding the EVM 

    Please note that we do not consider our hardware platforms to be a reference design. They are evaluation platforms and may not represent a proper system implementation.
    Our EVM design sometimes out paces our ability to fully understand device requirements. This is done so the hardware platform is available when first silicon arrives. We may learn new device requirements during processor bring-up and bench validation. If so, these new requirements may not be accounted for in our hardware development platform. Therefore, TI expects customers to carefully review and follow all requirements defined in the datasheet, silicon errata, and TRM when designing their system. Our hardware development platforms were not designed to be comprehensive of specific system requirements

    Regards,

    Sreenivasa