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DM8148 OCMC SIZE

xiongwei huang
Prodigy 100 points

Hi all

I read reference manual from http://www.ti.com/lit/ug/sprugz8/sprugz8.pdf page 123

this page says the ocmc from 0x40400000h will use to download image when use Peripheral Boot

but in

http://www.ti.com/lit/ds/symlink/tms320dm8148.pdf 

This address is resolved

And from http://www.ti.com/lit/ds/symlink/tms320c6a8168.pdf page 26 says this is the other 128k ocmc sram

Can I consider that the dm8148 also have the 256K SRAM ? the 40400000h address is useable for the ocmc sram just same as 8168 ? 

 

thanks and best regards

  • 0
    TI__Expert 8260 points

    Thannks for catching this.

    Its a bug in the DM814x Technical Reference Manual. The DM814x data sheet is correct. There is only 128KB of OCMC on DM814x at 0x40300000 and 0x40400000 is resered.

    The bug in the DM814x Technical Reference Manual will be fixed in the next revision.

    Regards, Srirami.

  • 0 in reply to srirami
    TI__Expert 8260 points

    Follwoing corrections will be taken care in the next revision of DM814X TRM:

    1.       The section 1.8.2 has to be modified as follows.

     

    1.8.2 Boot Image Location and Size

    The boot image is downloaded directly into internal RAM at the location 40300000h. The maximum size of

    downloaded image is 110KB

     

    2.       In the Figure 1-23. Peripheral Booting Procedure ,

     

    “Transfer Control to 0x4040000”   has to be changed to “Transfer Control to 0x4030000”

     

    3.       Table 1-35. PCIe BAR Window Base Address and Offset Configuration

    _____________________________________________________________

                  BAR                          Base Address     Offset                                 Comments

    _____________________________________________________________

    0                              0000 0000h         0000 0000h

    1 (64bit BAR0)    4000 0000h         4030 0000h                          OCMC RAM

    2                              6000 0000h          5000 0000h                          GPMC

    3 (64 Bit BAR2)   8000 0000h         8000 0000h                         DDR 0

    4                              a000 0000h          C000 0000h                        DDR 1

    Regards, Srirami.