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TCP3E Performance problem in Sync Buffer Mode

Faraday8303
Intellectual 310 points

Hi

I'm using C66x PDK and running the test project given for TCP3E. It was supposed to get higher throughput for method using sync buffer compared to pairwise method and chaining without sync buffer, but I'm getting lower throughput compared to other two cases.

I ran it on cyclic approximate simulator as well as EVM.

Why is it so?

 

Regards

 

  • 0
    TI__Intellectual 1260 points

    Why do you think the case using sync buffer gives you better performance?

    The primary difference is in the sync trigger mechanism implementation for next block in a magazine. The case using sync buffer is a bit complex which involves multiple writes to CPINTC register for generating events to the selected EDMA channels and eventually gets the sync trigger for the next block. It would easily add more delay in system.

  • 0 in reply to ravikorada
    Intellectual 310 points

    Dear Ravi,

    Thank you so much for your quick reply.

    The way it is explained in TCP3E SDS confused me. It is given that, in the sync buffer method CBs are maximally pipe lined.Also the timing diagrams given shows that sync buffer method finishes job fast.

    I didn't know about the extra delay due to complexity.

    Thanks again

     

    Best Regards

     

     

     

  • 0 in reply to ravikorada
    Intellectual 830 points

    Hi,

    I read your post coincidently. And I had some question about TCP3e module in 6670.

    By reading TCP3e User's Guide, I can see that if you input 1 bit, then you got 3 bits. There is a picture in the user's guide which describe the process of encoding. Here

    is my question: after encoding, the info bits of the encoded bits are placed together and parity bits are placed together. Why? And EDMA put them in the correct order

    which is one bit info bit and two parity  bits?

    And what's the relationship between transfer block and code block?

    Thank you very much

    Nick