Hi,
I'm using the C6747. The McASP 0 will receive and send data @ 48 kHz. These data streams are continuous. I also want to use a UART Tx to send packets of data. These packets will contain up to 350 bytes @ 115200 kbps and sent at every 35 to 40 ms (the UART will be used about 75% of the time).
The EDMA has two transfer controllers (TC) in this chip. I was thinking of associating the McASP 0 Rx with queue/TC0 and McASP 0 Tx with queue/TC1. Both of these transfers would use A-synchronization. Furthermore, I plan on using linked packets for both Rx and Tx to write/read to the internal input/output buffers in SRAM since the streams are continuous. Hence, the "completion rate" depends on buffer size (ACNT*BCNT*CCNT) and in my case these are relatively large. The completion interrupts would be well spaced out.
To minimize CPU intervention, I also want to use the EDMA to service the UART Tx.
I read through many EDMA-related documents and my understanding is that since I'm occupying both TC0 and TC1 continuously, any other transfer request that has a lengthy duration (the UART in my case) will cause an overrun/underrun of the McASP Rx or Tx (depending on which queue is used for the UART). When the McASP Rx/Tx terminates, the linked McASP transfer requests will be queued but since the UART transfer request is already in the queue, the UART transfer request will be sent to the TC before thereby stalling the next McASP transfer request. Are my observations exact?
To avoid this situation, I think I need to split my transfers into small packets thereby augmenting the completion rate and allowing the McASP Rx, McASP Tx and UART Tx transfer requests to be interleaved. I know that this will drastically reduce the EDMA utilization percentage because of overhead but do I have a choice? If I don't want to have McASP and UART overruns/underruns, I was thinking of doing single-element transfers (1 data word for the McASP and 1 byte for the UART) where BCNT=CCNT=1. The only way I think I can do this is to modify the next transfer request by updating the DMA channel's link PaRAM destination/source address registers to point to the next buffer locations (otherwise I will always read/write at the buffer base address). This would have to be done in the transfer completion interrupt. Is this the way it has to be done to make it work?
By the way, maybe it would be best to use queue 0 for single-word McASP Rx and Tx transfers and use the other queue solely for UART Tx thereby letting the EDMA take care of the whole packet instead of operating on a single-byte basis. What to you think?
Best regards,
SC
