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[FAQ] AM6442: use of 2x RMII EPHY for CPSW

HS FAE Germany
Mastermind 32710 points

Part Number: AM6442

Hello,
customer wants to use 2x RMII EPHY (DP83826) in slave mode for CPSW. What design/layout challenges does he need to take care? What clock buffer do we recommend to source the common clock for the RMII EPHY and AM64xx?

Regards, Holger

  • 0
    TI__Intellectual 1440 points

    Hi,

    is it possible to use the following clock buffer for the RMII-50MHz clock provided by the Sitara?

    https://www.ti.com/product/LMK1C1103

    One output will be routed back to the Sitara RMII-REF pin used for both RMII-Interfaces of CPSW3G

    The remaining two outputs will be routed to the respective XI-pins of DP83826 and all three outputs need to be length-matched, right?

  • 0 in reply to Walter Ahrend
    TI__Guru 63925 points

    I believe this can be done with the low skew clock buffer mentioned above. However, it will require careful PCB layout to ensure all timing requirements have margin. The tricky one you need to watch is the MAC min output delay of 2ns and the PHY hold time of 2ns. The PCB delay of the MAC to PHY data path will provide some margin, but it needs to be at least 50ps to account for the max clock buffer skew. You could also place the clock buffer closer to the two PHYs, such that the PHYs see the clock before the MAC. This would add additional margin for this parameter. However, this clock delay difference will impact the margin of other timing parameters. You need to do a careful timing analysis that includes all trace and clock path delays and adjust your PCB delays such that all timing requirements have margin.

    Since both AM64x RMII ports use a common clock, you need to make sure the PCB paths between AM64x and both PHYs have matched delays.

    Regards,
    Paul  

  • 0 in reply to peaves
    Prodigy 140 points

    Hello Paul,

    We are working on a very similar setup with the RMII clock provided by the CLKOUT of the AM6442, but with only one PHY.

    Do we actually need a clock buffer in this case or can the CLKOUT of the AM6442 drive both clock pins like in the picture above? The length between CLKOUT->PYH and CLKOUT->MAC should be matched of course.

    Could you also please elaborate on your explanation above regarding the clock skew? Because, to be honest, I can't quite follow your explanation? Why is the low skew of the clock buffer "bad", making the PCB layout more tricky? How is the data path delay connected to the clock buffer skew? The data is set on the falling edge and sampled on the rising edge of the clock:

    So as long as T2 and T3 are "long enough" there should be no problem. The clock period is 20ns, 50ps clock skew should not significantly influence the timing.

    Thank you very much in advance!

    Regards,
    Stefan

  • 0 in reply to Stefan Glaser2
    TI__Mastermind 41250 points

    Hi, 

    I will check on your question tomorrow.

    Best Regards,

    Schuyler

  • 0 in reply to Stefan Glaser2
    TI__Guru 63925 points

    I would not recommend sourcing two loads with a single clock source. There will be an impedance discontinuity when the signal splits into two paths and this will create reflections that distorts the clock signal. The distortion could cause glitches on the internal clocks of the MAC and PHY. There may be tricks you can do on your PCB to minimize the reflections, but you would need to simulate signal integrity of your specific PCB design to be sure the implementation will not cause problems. Adding the low skew clock buffer is the best approach.

    I never said the low skew buffer was a problem. You actually need a low skew buffer to make this work.

    Let's assume you match the length of each clock path. The clock buffer could insert as much as 50ps of skew, so the PHY could receive the clock 50ps after the MAC.  This could be a problem because the PHY has a 2ns hold time requirement and the MAC may only hold the previous data value for 2ns. It takes some time for the MAC output data to reach the PHY because the of the data path delay.  However, this data path delay must be greater than 50ps to ensure the data arriving at the PHY does not violate its hold time requirement. If the data path is not at least 50ps long, you would need to make it longer, or shorten the clock delay to the to the PHY relative to the clock delay to the MAC. This would add additional margin to the PHY hold time requirement. However, it removes setup time margin.

    Setup time is a function of clock period since data is changed on the rising edge of clock and latched on the next rising edge of clock. Hold time is not a function of clock period since data must be held for a specific period of time after the clock edge that latches data.

    Regards,
    Paul