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SDL BIST example application halts midway (at the PBIST failure insertion test for Main R5F 1) during execution and fails on SDK 8.6.
The fix to this issue is a two step process -
1. Changes to be made to the source code:
a. A re-alignment of the boot stages and the PBIST instances is required in the sdl/examples/bist/bist_core_defs.c file.
b. The numPostPbistToCheck parameter must be added to the PBIST_TestHandleArray present in sdl/examples/bist/bist_core_defs.h file.
c. Few changes to be made to update the PBIST APIs in sdl/examples/bist/bist.c, sdl/examples/bist/pbist_utils.c, sdl/examples/bist/pbist_utils.h and sdl/examples/bist/soc/j721e/pbist_defs.c
Please follow the patch below for these changes (included in the SDK 9.0), using the following commands -
cd $RTOS_SDK/sdl/
git init
git add .
git commit -m "init commit"
git am $PATH_TO_PATCH_SHARED_BELOW
From b049464fa3077342479d17bb078f4633f448e004 Mon Sep 17 00:00:00 2001
From: Josiitaa RL <j-rl@ti.com>
Date: Fri, 6 Oct 2023 13:27:26 +0530
Subject: [PATCH] Fixed: SDL BIST Example Application failure
- Re-alignment of the boot stages and the PBIST instances.
- The numPostPbistToCheck parameter added to the PBIST_TestHandleArray.
- Few code changes made to update the PBIST APIs.
Signed-off-by: Josiitaa RL <j-rl@ti.com>
---
examples/bist/bist.c | 8 ++++----
examples/bist/pbist_utils.c | 25 ++++++++++++++++--------
examples/bist/pbist_utils.h | 2 +-
examples/bist/soc/j721e/bist_core_defs.c | 19 +++++-------------
examples/bist/soc/j721e/bist_core_defs.h | 2 +-
examples/bist/soc/j721e/pbist_defs.c | 1 +
6 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/examples/bist/bist.c b/examples/bist/bist.c
index 61d7efb..aff2da9 100644
--- a/examples/bist/bist.c
+++ b/examples/bist/bist.c
@@ -172,7 +172,7 @@ void bist_TaskFxn(void)
for (i = 0; i < num_pbists_pre_boot; i++)
{
/* Run test on selected instance */
- testResult = PBIST_runTest(pbist_pre_boot_stage[i], true);
+ testResult = PBIST_runTest(pbist_pre_boot_stage[i],(uint8_t)1);
/* Convert signed return value (with -1 = failure and 0 = pass) to become
* 0 = failure and 1 = pass */
pbist_pre_boot_stage_neg_status[i] = testResult + 1;
@@ -187,7 +187,7 @@ void bist_TaskFxn(void)
for (i = 0; i < num_pbists_pre_boot; i++)
{
/* Run test on selected instance */
- testResult = PBIST_runTest(pbist_pre_boot_stage[i], false);
+ testResult = PBIST_runTest(pbist_pre_boot_stage[i],(uint8_t)0);
/* Convert signed return value (with -1 = failure and 0 = pass) to become
* 0 = failure and 1 = pass */
pbist_pre_boot_stage_status[i] = testResult + 1;
@@ -236,7 +236,7 @@ void bist_TaskFxn(void)
PBIST_clecConfig(pbist_array[i]);
/* Run test on selected instance */
- testResult = PBIST_runTest(pbist_array[i], true);
+ testResult = PBIST_runTest(pbist_array[i], (uint8_t)1);
/* Convert signed return value (with -1 = failure and 0 = pass) to become
* a single bit as part of bitfield with 0 = failure and 1 = pass */
@@ -252,7 +252,7 @@ void bist_TaskFxn(void)
for (i = 0; i < num_pbists_per_boot_stage[j]; i++)
{
/* Run test on selected instance */
- testResult = PBIST_runTest(pbist_array[i], false);
+ testResult = PBIST_runTest(pbist_array[i], (uint8_t)0);
/* Convert signed return value (with -1 = failure and 0 = pass) to become
* a single bit as part of bitfield with 0 = failure and 1 = pass */
diff --git a/examples/bist/pbist_utils.c b/examples/bist/pbist_utils.c
index feca043..439afd3 100644
--- a/examples/bist/pbist_utils.c
+++ b/examples/bist/pbist_utils.c
@@ -141,6 +141,10 @@
/* ========================================================================== */
/* PBIST_setFirewall: Sets firewall settings to be able to access CLEC registers */
+
+#if defined(SOC_J721E) || defined(SOC_J721S2)|| defined(SOC_J784S4)
+
+
static int32_t PBIST_setFirewall(void)
{
int32_t retVal = CSL_PASS;
@@ -149,8 +153,9 @@ static int32_t PBIST_setFirewall(void)
struct tisci_msg_fwl_set_firewall_region_req request;
Sciclient_ReqPrm_t reqParam = {0};
Sciclient_RespPrm_t respParam = {0};
-
+ #if defined(SOC_J721E)
request.fwl_id = (uint32_t)CSL_STD_FW_NAVSS0_NAV_SRAM0_ID;
+ #endif
request.region = (uint32_t) 1U; /* Pick up any unused region : 1 */
request.n_permission_regs = CSL_FW_NUM_CBASS_FW_EP_REGION_PERMISSION;
request.control = (FW_REGION_ENABLE & CSL_CBASS_ISC_EP_REGION_CONTROL_ENABLE_MASK);
@@ -236,13 +241,13 @@ static int32_t PBIST_setFirewall(void)
}
return retVal;
}
-
+#endif
int32_t SDL_OSAL_getClecOutputEvent(uint32_t *clecOutputEvt)
{
int32_t retVal = SDL_PASS;
-
+#if defined(SOC_J721E) || defined(SOC_J721S2)
*clecOutputEvt = CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12;
-
+#endif
return retVal;
}
@@ -254,6 +259,7 @@ int32_t SDL_OSAL_releaseClecOutputEvent(uint32_t clecOutputEvt)
/* CLEC configuration for C7X and A72 instances */
int32_t PBIST_clecConfig(uint32_t instance)
{
+ #if defined(SOC_J721E)
SDL_ErrType_t status = SDL_EFAIL;
CSL_ClecEventConfig evtCfg;
@@ -288,12 +294,14 @@ int32_t PBIST_clecConfig(uint32_t instance)
}
return status;
+#endif
}
/* Captures common Initialization: currently initializes CLEC interrupt routing
for C7x & A72 */
int32_t PBIST_commonInit(void)
{
+ #if defined(SOC_J721E) || defined(SOC_J721S2)|| defined(SOC_J784S4)
CSL_ErrType_t status;
int32_t retValue = 0;
@@ -306,6 +314,7 @@ int32_t PBIST_commonInit(void)
}
return status;
+#endif
}
@@ -323,11 +332,11 @@ int32_t PBIST_commonInit(void)
* Step 4: Restore cores
* */
-int32_t PBIST_runTest(uint32_t instanceId, bool runNegTest)
+int32_t PBIST_runTest(uint32_t instanceId, uint8_t test)
{
int32_t testResult = 0;
SDL_ErrType_t status;
- bool PBISTResult;
+ bool PBISTResult = true;
SDL_PBIST_testType testType;
uint32_t i = 0;
@@ -340,7 +349,7 @@ int32_t PBIST_runTest(uint32_t instanceId, bool runNegTest)
uint64_t prepTime, diffTime, restoreTime;
#endif
- if (runNegTest == true)
+ if (test == 1u)
{
UART_printf("\n Starting PBIST failure insertion test on %s, index %d...\n",
PBIST_TestHandleArray[instanceId].testName,
@@ -364,7 +373,7 @@ int32_t PBIST_runTest(uint32_t instanceId, bool runNegTest)
if ((testResult == 0) &&
(PBIST_TestHandleArray[instanceId].numPostPbistToCheck > 0))
{
- if (runNegTest == false)
+ if (test == 0u)
{
#ifdef DEBUG
UART_printf(" HW POST: Running test on HW POST, %d Instances \n",
diff --git a/examples/bist/pbist_utils.h b/examples/bist/pbist_utils.h
index 7a805f8..8d27083 100644
--- a/examples/bist/pbist_utils.h
+++ b/examples/bist/pbist_utils.h
@@ -84,6 +84,6 @@
/* ========================================================================== */
int32_t PBIST_clecConfig(uint32_t instance);
int32_t PBIST_commonInit(void);
-int32_t PBIST_runTest(uint32_t instanceId, bool runNegTest);
+int32_t PBIST_runTest(uint32_t instanceId, uint8_t test);
#endif /* PBIST_UTILS_H_ */
diff --git a/examples/bist/soc/j721e/bist_core_defs.c b/examples/bist/soc/j721e/bist_core_defs.c
index 46a7575..6396d85 100644
--- a/examples/bist/soc/j721e/bist_core_defs.c
+++ b/examples/bist/soc/j721e/bist_core_defs.c
@@ -162,7 +162,11 @@ int pbist_second_boot_stage[] =
PBIST_INSTANCE_C66X_0, /* C6X core 0 */
PBIST_INSTANCE_C66X_1, /* C6X core 1 */
PBIST_INSTANCE_VPAC, /* VPAC */
- PBIST_INSTANCE_DMPAC /* DMPAC */
+ PBIST_INSTANCE_DMPAC, /* DMPAC */
+ PBIST_INSTANCE_A72, /* A72 */
+ PBIST_INSTANCE_HC, /* HC - MLB PBIST */
+ PBIST_INSTANCE_ENCODER, /* Encoder */
+ PBIST_INSTANCE_DECODER
};
/* Defines LBIST's for the second stage of the Main Domain
@@ -175,17 +179,6 @@ int lbist_second_boot_stage[] =
LBIST_DMPAC_INDEX /* DMPAC */
};
-/* Defines PBIST's for the third stage of the Main Domain
- * boot sequence for J721E SOC */
-int pbist_third_boot_stage[] =
-{
- PBIST_INSTANCE_A72, /* A72 */
- PBIST_INSTANCE_HC, /* HC - MLB PBIST */
- PBIST_INSTANCE_ENCODER, /* Encoder */
- PBIST_INSTANCE_DECODER /* Decoder */
-};
-
-
/* Defines LBIST's for the third stage of the Main Domain
* boot sequence for J721E SOC */
int lbist_third_boot_stage[] =
@@ -198,7 +191,6 @@ int *pbist_array_stage[NUM_BOOT_STAGES] =
{
pbist_first_boot_stage,
pbist_second_boot_stage,
- pbist_third_boot_stage
};
/* Points to lbist arrays for each of the boot stages */
@@ -222,7 +214,6 @@ uint8_t num_pbists_per_boot_stage[NUM_BOOT_STAGES] =
{
sizeof(pbist_first_boot_stage) / sizeof(int),
sizeof(pbist_second_boot_stage) / sizeof(int),
- sizeof(pbist_third_boot_stage) / sizeof(int)
};
uint8_t num_lbists_pre_boot = sizeof(lbist_pre_boot_stage) / sizeof(int);
diff --git a/examples/bist/soc/j721e/bist_core_defs.h b/examples/bist/soc/j721e/bist_core_defs.h
index 6f547c5..e1d155b 100644
--- a/examples/bist/soc/j721e/bist_core_defs.h
+++ b/examples/bist/soc/j721e/bist_core_defs.h
@@ -74,7 +74,7 @@ extern "C"
#define PBIST_MAX_INSTANCE (PBIST_INSTANCE_MCU_PULSAR+1U)
-#define PBIST_INSTANCE_NAME_MAX_LENGTH 16
+#define PBIST_INSTANCE_NAME_MAX_LENGTH 20
#define LBIST_HWPOST_DMSC_INDEX 0
#define LBIST_HWPOST_MCU_INDEX 1
diff --git a/examples/bist/soc/j721e/pbist_defs.c b/examples/bist/soc/j721e/pbist_defs.c
index 8a92d36..cd61405 100755
--- a/examples/bist/soc/j721e/pbist_defs.c
+++ b/examples/bist/soc/j721e/pbist_defs.c
@@ -281,6 +281,7 @@ PBIST_TestHandle_t PBIST_TestHandleArray[PBIST_MAX_INSTANCE+1] =
{
.testName = "A72 PBIST",
.pbistInst = SDL_PBIST_INST_A72,
+ .numPostPbistToCheck = 0u,
.tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_PBIST_WRAP, /* Device Id for A72 PBIST */
.procRstNeeded = true,
.secondaryCoreNeeded = true, /* Secondary core needed */
--
2.34.1
2. Multicore app image must be loaded:
Starting with SDK 8.6.0, MCU R5F boots in non-secure mode, therefore, the BIST example requires a multicore app image to be loaded. The reason for using the multicore app image (R5F and C7X binary) is to make sure MCU R5F is able to do CLEC configuration.This image is genarated in the same folder as the binary is generated. The multi core app image binary file is named as bist_example_app_r5f_baremetal_multicore_image.appimage.
Regards,
Josiitaa