AM625: AM62x dss pixel clock

Tran Thang

Part Number: AM625

Dear TI.

I use am62 and output dss via DPI and LVDS, we must set fps exactly to 60fps but we actual got 59.98 fps on LVDS

In my investigate DSS pixel clock not accept any rate, when I set clock rate for DPI to 12702000 and LVDS to 88914000 I got clock by clk_get_rate() and get actual rate 12,701,612 and 88,888,888

So I want to know what clock can we set without difference

Thank for your support.

over 1 year ago

0 Krunal Bhargav34 over 1 year ago

TI__Mastermind 43735 points

Hello,

Let me check internally and get back to you.

Regards,
Krunal

0 Krunal Bhargav34 over 1 year ago in reply to Krunal Bhargav34

TI__Mastermind 43735 points

Hello,

Could you try to set the clock using following methods to set clock:

k3conf set clock 186 0 <freq in Hz> for LVDS

k3conf set clock 186 2 <freq in Hz> for DPI / HDMI

I was also given a experimental patch from the dev team that you can try:

Fullscreen

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
index d4b4e74e22da..80a929c98771 100644
--- a/drivers/clk/keystone/sci-clk.c
+++ b/drivers/clk/keystone/sci-clk.c
@@ -176,13 +176,28 @@ static int sci_clk_determine_rate(struct clk_hw *hw,
         return 0;
     }
 
+    /* Check for exact frequency first */
     ret = clk->provider->ops->get_best_match_freq(clk->provider->sci,
                               clk->dev_id,
                               clk->clk_id,
-                              req->min_rate,
                               req->rate,
-                              req->max_rate,
+                              req->rate,
+                              req->rate,
                               &new_rate);
+
+    if (ret) {
+        dev_dbg(clk->provider->dev,
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
index d4b4e74e22da..80a929c98771 100644
--- a/drivers/clk/keystone/sci-clk.c
+++ b/drivers/clk/keystone/sci-clk.c
@@ -176,13 +176,28 @@ static int sci_clk_determine_rate(struct clk_hw *hw,
         return 0;
     }
 
+    /* Check for exact frequency first */
     ret = clk->provider->ops->get_best_match_freq(clk->provider->sci,
                               clk->dev_id,
                               clk->clk_id,
-                              req->min_rate,
                               req->rate,
-                              req->max_rate,
+                              req->rate,
+                              req->rate,
                               &new_rate);
+
+    if (ret) {
+        dev_dbg(clk->provider->dev,
+            "exact determine-rate failed for dev=%d, clk=%d, ret=%d\n",
+            clk->dev_id, clk->clk_id, ret);
+        ret = clk->provider->ops->get_best_match_freq(clk->provider->sci,
+                            clk->dev_id,
+                            clk->clk_id,
+                            req->min_rate,
+                            req->rate,
+                            req->max_rate,
+                            &new_rate);
+    }
+
     if (ret) {
         dev_err(clk->provider->dev,
             "determine-rate failed for dev=%d, clk=%d, ret=%d\n",
@@ -211,10 +226,22 @@ static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
                 unsigned long parent_rate)
 {
     struct sci_clk *clk = to_sci_clk(hw);
+    int ret;
+
+    /* Try setting exact frequency first */
+    ret = clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
+                       clk->clk_id, rate, rate,
+                       rate);
+    if (ret) {
+        dev_dbg(clk->provider->dev,
+            "exact set-rate failed for dev=%d, clk=%d, ret=%d\n",
+            clk->dev_id, clk->clk_id, ret);
+        return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
+                            clk->clk_id, rate / 10 * 9, rate,
+                            rate / 10 * 11);
+    }
 
-    return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
-                        clk->clk_id, rate / 10 * 9, rate,
-                        rate / 10 * 11);
+    return ret;
 }
 
 /**

Regards,

Krunal

0 Tran Thang over 1 year ago in reply to Krunal Bhargav34

Prodigy 120 points

I modify clock driver as you suggestion and it can work now. Thanks for your support

Processors

Processors forum

AM625: AM62x dss pixel clock