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AM625: Jailhouse Support--Splitting GPIOs between cells

Ryan T
Expert 3161 points
Part Number: AM625


Hi Team, 

In the current implementation of Jailhouse in our SDK, is it possible to split GPIOs between different VMs of Jailhouse? For example, main_gpio0 to root cell and main_gpio1 to non-root cell?

Do any examples of this exist that a customer can refer to?

Best regards,

-Ryan

  • 0
    TI__Guru 70037 points

    Hi Ryan,

    you could split different (distinct) GPIO peripheral modules the same way you can assign other peripheral modules to a particular root cell / inmate instance. We don't have a GPIO-specific example at this time, and doing a quick online search I also can't see any ready-to-use steps. On a high level you'd need to review and customize the following files:

    • <jailhouse_src_root>/configs/arm64/k3-am625-sk.c to remove one GPIO module from the existing GPIO definition
    • <jailhouse_src_root>/configs/arm64/k3-am625-sk-linux-demo.c to add one GPIO module
    • <jailhouse_src_root>/configs/arm64/dts/inmate-k3-am625-sk.dts to add one GPIO module
    • <linux_kernel_src_root>/arch/arm64/boot/dts/ti/k3-am625-sk.dts to remove/disable one GPIO module

    Similar steps should apply to pretty much all such peripheral-partitioning/assignment type of changes.

    Regards, Andreas

  • 0 in reply to Andreas Dannenberg
    TI__Expert 3161 points

    Hi Andreas, 

    My customer has tried these steps, but the problem arises in trying to split the interrupt router: 

    How should this be configured wherein both for root-cell and a non-root linux cell has access to this? Because according to the data sheet, all GPIO interrupts are routed through this.

    It looks like there's an example for a different platform from our lineup (k3-j721e) which has split the GPIOs and the corresponding interrupt router: https://github.com/siemens/jailhouse/blob/master/configs/arm64/dts/inmate-k3-j721e-evm.dts

    Can something similar be achieved for AM62?

    BR,

    RT

  • 0 in reply to Ryan T
    TI__Guru 70037 points
    Ryan T said:
    Can something similar be achieved for AM62?

    You should be able to do the same thing. The interrupt routing and aggregation on TI K3 SoCs like AM62, J721E, etc. is managed through the TI System Controller interface (https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html) so the interrupt controllers don't really need to be concerned about memory-mapped interrupt from a Linux POV, which is probably the reason the "reg = <...>" DTS note isn't even specified.

    Regards, Andreas