I am trying to understand the Cache performance of c6747 DSP. When I try out I get same no. cycles when memory is accessed First time and later. How is it possible. How do I confirm that Cache is working?
If I set the L1DCFG to 0K memory setting, then there is no change in the number of cycles. I still get same number of cycles.
Can anyone explain how to derive it. I need these metrics to evaluate the number of additional MIPS required for the overall voip algorithms because of memory accesses.
Regards,
Hari
#pragma CODE_SECTION(testWrite, ".L1Code:testWrite")
void testWrite(char *pBuf, int len)
{
register int i;
register int *ptr = (int *) pBuf;
for (i=0;i<len/4;i++)
{
ptr[i]=i;
}
}
#pragma CODE_SECTION(testRead, ".L1Code:testRead")
void testRead(char *pBuf, int len)
{
register int i,j;
register int *ptr = (int *) pBuf;
for (i=0;i<len/4;i++)
{
j=ptr[i];
}
}
main()
{
BCACHE_wbInvAll(); // 7.7K cycles
// testWrite(Externbuf,SIZE_OF_ARR);
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testWrite(Externbuf,SIZE_OF_ARR);// 20K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testWrite(Externbuf,SIZE_OF_ARR);// 20K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
testWrite(Externbuf,SIZE_OF_ARR);// 20K cycles for 4K byte array
testRead(Externbuf,SIZE_OF_ARR);// 17K cycles for 4K byte array
}
