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TDA4VH-Q1: Connection of TDA4VH SERDES0/1 interface clock

Cherry Zhou
Mastermind 22235 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH

Hi Team,

In the TDA4VH development board reference design, SERDES1 is used to connect to PCIe x4 lane CONN and SERDES0 is used to connect to PCIe x2 lane CONN as well as USBC.

1) 

a. The reference clock SERDES1_REFCLK for SERDES1 is used to receive the clock signal. PCIe_REFCLK0_P/N_out is disconnected. (0ohm resistor in BOM is DNI)

b. The reference clock SERDES0_REFCLK for SERDES0 is disconnected (0ohm resistor in BOM is DNI). PCIE_REFCLK1_P/N_out is connected to the clock input.

Would you help share the intention of the above connections? Also, could you help share how to use a reference clock?

2) How to set the reference clock if the customer want to use SERDES0_TX2/RX2 from SERDES0 as SSTX/RX for USB A?

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Guru 62460 points

    Cherry,

    The device TDA4VH supports dual internal ref clk  (INT0 and INT1). For PCIe, 100MHz internal ref clk is supported and USB uses 100MHz as well.

    you can use internal SSC (spread spectrum clocking) on the ref clk for USB.

  • 0 in reply to ShreyasRao
    TI__Guru 53015 points

    External REFCLKs can be used if additional reference clocks are needed (beyond what can be supported internally) or for PCIe configurations where Host and EndPoint share the same reference clock.  For this designs can have external clock generator that source clock to both devices.