Hi,
I have a question about the DM365 BOXCAR averaging engine. To allow the engine to write its results to the SDRAM, the Buffer Logic control register DDR multiplexer bits need to be set up (see section 6.6.3 in the VPFE guide sprufg8c.pdf). The guide states that Bit 0 selects between BOXCAR and LDC access, and Bit 1 selects between ISIF and BOXCAR access. I found by experimentation the BOXCAR will only write its results when BOXCAR is enabled by setting Bit 0 to 1. Writing 0 to Bit 1 does not seem to allow the BOXCAR to write its results. Could you please tell me if this is an errata in the guide, or am I misunderstanding something? We would like to run BOXCAR and LDC together at some point (in parallel with normal IPIPE single shot operation), will that be possible?