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AM6442: DDR tck margin and speed change

Jason Reeder
Genius 10440 points
Part Number: AM6442

Customer says:

We want to have additional margin for DDR. We saw tck (clock cycle time) slightly fail.

JEDEC and DDR4 datasheet specify tck 1.25-1.5ns for 1600MT/s DDR4.

Out measurement value is 1.2497ns which is slightly below the min value of 1.25ns.

  • What is the max possible deviation of PLL clock frequency?
  • Is it possible to set AM64xx DDR clock to 780MHz nominal instead of 800MHz?
  • Can you provide the register dump (or how to get it) of AM64xx PLL 12?
  • 0
    TI__Guru 63125 points

    The PLL that sources this clock has variations that were accounted for during timing closure of the device. Therefore, you do not need to reduce the frequency to account for the datasheet minimum clock period. The datasheet minimum value is the mean frequency limit.

    There are no plans to define the PLL variation. 

    Regards,
    Paul