AM3730 Technical Reference Manual said:
The IVA2.2 MMU main features are:
• 32 entries/fully associative translation lookaside buffer (TLB)
SPRUGN4I–May 2010–Revised March 2011 IVA2.2 Subsystem 711
• One interrupt line to the MPU
• 32-bit virtual addresses, 32-bit physical addresses
• 4-KB and 64-KB pages, 1-MB section, 16-MB supersection
• Predefined (static), software-driven (interrupt-based) or table-driven (hardware table-walker) software
translation strategies
WIKI:OMAP3_DSP_MMU_Configuration said:
- There are only 31 TLB entries locked for 4KB, 64KB, 1MB, and 16MB contiguous memory regions.
- Memory segments must be a multiple of 4KB.
- Adjacent memory must add up to a multiple of 4KB. Note smaller adjacent memory regions are grouped into a larger region which optimizes the number of TLB entries.
where is the other one TLB entry ?Please tell me !Thanks!