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Regarding Operating Frequency

1258021
Genius 5120 points

Other Parts Discussed in Thread: OMAP-L138

Hi,

We are using 1.2V Core Voltage for the OMAP-L138. This means OMAP-l138 can run upto 375MHz frequency.

In our current software I know that OMAP-L138 ARM is running at 300 MHz frequency.

Our requirement is one of the LCD panel that is connected to OMAP-L138 need Pixel Clock in the range of 32MHz to 34.5 MHz.

As SYSCLK2 drives the LCD_CLK for LCD Module we are thinking that we have to reduce the ARM frequency to 276MHz.

So that SYSCLK2 = 138MHz and if we program CLKDIV in LCD_CTRL to 3 then we get the required range of frequency of operation for LCD Panel.

Is my understanding is correct?

Regards,

GSR

  • 0
    TI__Mastermind 27585 points

    Yes you are correct in your understanding. That should get you to 34.5 MHz

    Jeff

  • 0 in reply to jc-ti
    Genius 5120 points

    Hi,

    I know that the core voltage is 1.2V so OMAP-L138 maximum frequency can be 375MHz.

    to get the required frequency can we increase it to 320MHz? Reference clock that we are using is 24MHz...

    Apart from this I know that EMIFA max operating frequency is 100MHz. In one place can I get what are the maximum operating frequencies for the Peripherals which are clcockd from PLLC0.SYSCLK[1:7]?

    Regards,

    GSR

  • 0 in reply to 1258021
    Genius 5120 points

    Hi,

    Is there any relation between VCLK and 2X_CLK.

    What is the minimum value and maximum values for VLCK?

    VCLK is referred from System Reference Guide Page number 76.

    Regards,

    GSR

  • 0 in reply to 1258021
    Genius 5120 points

    Hi,

    We have changed ARM frequency from 300MHz to 336MHz.

    With this I have observed that PLLC0.SYSCLK5 changed from 100MHz to 112MHz.

    Values in MHz EVM Clocks Custom HW Clocks
    Reference Clock 24 24
    PLL0 300 336
    SYSCLK1 300 336
    SYSCLK2 150 168
    SYSCLK3 100 84
    SYSCLK4 75 84
    SYSCLK5 100 112
    SYSCLK6 300 336
    SYSCLK7 50 56
    AUXCLK 24 24
    PLL1 264 264
    SYSCLK1 264 264
    SYSCLK2 132 132
    SYSCLK3 88 88

    The above table provides the frequencies in MHz after changing ARM frequency to 336Mhz.

    Can some tell will there be any impact on SDRAM. Do we have to change the existing SDRAM timing values since SYSCLK2 increased to 168MHz from 150mHz?

    Please guide us.

    Regards,

    GSR

  • 0 in reply to 1258021
    TI__Mastermind 27585 points

    Do you mean the DDR2 SDRAM or the EMIFA SDRAM? The DDR2 is only supported up to 150 MHz so you will not be able to run at 168 MHz if that is the case.

    If you do change the DDR frequency, the timing numbers have to be updated as well.

    Jeff

  • 0 in reply to jc-ti
    Genius 5120 points

    Hi Jeff,

    Thank you for the reply. Basically we are using the SOM from LogicPD and we have changed the baseboard for our customization.

    We are using the DDR present on SOM only.

    When we increase processor clock from 300MHz to 336MHz VLCK=PLLC0.SYSCLK2 which has increased from 150MHz to 168MHz.

    If we see the table that I had given in my previous post PLLC1.SYSCLK1 is not changed and set to 264MHz which is used as 2X_CLK for SDRAM

    While calculating timing parameters in CCS UBL code, it looks they have considered only 132MHz and not the 168MHz (VLCK).

    What is the maximum allowed frequency for VLCK?

    As we have changed only VLCK and not DDR_CLK my understanding is we need not to calculate timing parameters.

    I also observe that SYSCLK5.PLLC0 increased to 112MHz. What are the limitations for SYSCLK5?

    Please let me know if my understanding is correct. Thanks for your time.

    Regards,

    GSR

  • 0 in reply to 1258021
    TI__Mastermind 27585 points

    Yes you are correct, as long as the DDR output clock hasn't changed then you do not need to update the controller timings.

    PLL0_SYSCLK5 is not used in this device so there is no specific limitation for that clock.

    Jeff