TDA4VM: the Rounting skew requirement for LPDDR4(4266Mbps) ofTDA4VM T-speed

Hi Juanli,

Can you please take a look at the following document and see if this answers your question?

https://www.ti.com/lit/pdf/spracn9

Regards,
Kevin

Hi Kevin,

Thanks for your support.

One more question is does the processor ** IO Buffer and DDR SDRAM ** IO buffer here refer to the DIE from TDA4's DDR DIE to the SDRAMs DIE? If so, could you provide the die-to-package delay time of TDA4 DDR?

Best Regards

Juanli Zhang

Attached are TDA4VM package delays for LPDDR4 nets.

TDA4VM_LPDDR4_Pkg_Delay.xlsx

Hi Robert,

Thank you.

Could you provide the TDA4 DDR timing parameters of 3200Mbps and 4266Mbps? Reference as below.

Best Regards

Juanli Zhang

Hi Juanli,

What version of the DDR Configuration Tool are you using?

regards

Suman

Hi Suman,

The DDR configuration tool revision is 0.10.0.

Best Regards

Juanli Zhang

Hi Suman,

I use the HyperLynx vx2.7 for LPDDR4 simulation. These parameters on the screenshot are needed in the simulation. So could you provide these parameters on 3200Mbps and 4266Mbs. Many thanks.

Best Regards

Juanli Zhang

We don't provide timing information for the LPDDR4 interface.  The interface is to be validated during design using the JEDEC eye masks provided in the application note previously referenced.

Hello Robert，

I see you sent the package delays for LDPPR net.

By the way ,I would like to confirm with if there are the same documents available for OSPI flash and EMMC net. Could you help check it for me?

Thank you!

No - we do not have package delay information for OSPI or EMMC interfaces.

Is it due to the very low rate for EMMC and FLASH than LPDDR?  So it is unnecessary consider the delay of tda4 chip itself separately?

Correct - package delay/skew is small enough that it shouldn't matter for these other interfaces.

Hi Robert,

In the IBIS model of J211E_DR829_TDA4VM.ibs, does the DDR go to the package or to the Die? Thank you.

Best Regards

Juanli Zhang