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AM335x - Disable L2 Cache

Lucas Cunha
Prodigy 10 points


So, I want to make some analysis with my L2 cache disabled. I'm running an U-boot environment, bare-metal, on my BeagleBone black and I'm trying to disable the cache following the steps provided on:

https://developer.arm.com/documentation/ddi0344/k/level-2-memory-system/enabling-and-disabling-the-l2-cache-controller

My code is something like this:

asm volatile("MRC p15, 0, %0, c1, c0, 0\t\n": "=r"(controlRegister)); //Retrieve Control Register
controlRegister = controlRegister & ~(1u << 2); //change Bit C to 0;
asm volatile ("MCR p15, 0, %0, c1, c0, 0\t\n" :: "r"(controlRegister)); //write new value

I know this is only the first step(disable C bit), but I'm having trouble accomplishing it. The problem is, when i try to write the new value and then check if it was write correctly, the value retrieved is 00000000.

I've been trying to enter the supervisor mode without any success, but then I decided to look on my current operation mode accessing the CPSR and checking the [4-0] bits, as mentioned  here . And, according to the CPSR I'm already on unsecured supervisor mode(10011), which seems to be a privileged mode. But I'm still unable to write effectively on Control Register (C1).

So I've tried to go from unsecured to secured mode, but according to the docs I can only access and change the NS-bit if I'm on a secure privileged mode.

My question is, how can I disable L2 cache, if I don't have a secure privileged mode access? For what i have searched the am335x does not allow TrustZone, which for what i understood is the equivalente of privileged secure mode.

So, there is no way to disable the L2 cache? Or I'm doing something wrong?

UPDATE: Adding some things that i've checked. On ARM's Documentation of Cortex-A8 it's said that I am supposed to be able to write on C1 register from an unsecure privileged mode (I'm on supervisor's mode, so that should be enough). When i try to write on C1 register, at this point, my program stays hanging and does not ends until the board restarts, the value that I'm trying to write is 0x00C50879, which is the equivalent of C and I bit disabled.

UPDATE 2: I don't know if it's relevant, but I'm using arm-none-eabi as my toolchain for compilling, and my code is being loaded on the address 0x80000000

Regards,

Lucas Cunha

  • 0
    TI__Guru 69900 points

    Hello Lucas,
    Please refer to <3.1.4.2.2 Secure Monitor Calls to Access CP15 Registers> in AM335x TRM
    www.ti.com/.../spruh73
    "The device supports special secure monitor functions that allows access to certain ARM core registers in
    privileged mode. Functions to write to the Auxiliary Control Register, Nonsecure Access Control Register,
    and the L2 Cache Auxiliary Control Register are provided (see the ARM Technical Reference Manual for a
    description of these registers)."
    Best,
    -Hong

  • 0 in reply to Hong Guan64
    Prodigy 10 points

    Hello Hong, thanks for the reply!

    Following the steps on ARM's Technical Reference, to disable the L2 cache I need to change the C-bit from ControlRegister(C1) and the L2EN-bit from Auxiliary Control Register(C1). None of them appears to be a secured bit so the Supervisor mode should be enough.

    When I try to change only the C-bit, with the code provided earlier, my program stays hanging until the board restarts.

    I've also tried to run ISB and DSB instructions for synchronization purposes, hoping that it could be the issue, but with no success.

    Do you have any idea or suggestion on how can I disable the L2 cache or what could be causing my program to stay hanging?

    Regards,

    Lucas

  • 0 in reply to Lucas Cunha
    TI__Guru 69900 points

    Hello Lucas,
    For your reference, I ran L2 cache testing using Lauterbach T32 JTAg debugger with Linux SDK 8.2 on AM335x EVM
    1/. stop @u-boot, L2 cache is enabled as shown below

    2/. I'm able to modify CP15 SCTLR and ACTLR directly via JTAG debugger as listed below

    Best,

    -Hong

  • 0 in reply to Hong Guan64
    Prodigy 10 points

    Hello Hong,

    Following your response, I've tried to run through the pre-built u-boot image from Linux SDK 8.2 provided here, but I got to the same result(the program hangs).

    Did you achieve it loading a .bin file and triggering it through u-boot?

    If so, could you provide me some infos about your environment so that I can try to replicate your result?

    1- which was the toolchain used for compilation?

    2- did you use any compilation flags?

    3- what was the address your program was load?

    4- did you create another file for some kind of initialization or configuration?

    5- if possible, could you provide the source code of your files?

    For context, I'm:

    1- loading the program on the address 0x80000000;

    2- using the arm-none-eabi toolchain for compile;

    3- using the following flags during compilation:

            -Wall -Werror -O2 -nostdlib -nostartfiles -ffreestanding -march=armv7-a -mtune=cortex-a8

    Regards,

    Lucas Cunha

  • 0 in reply to Lucas Cunha
    TI__Guru 69900 points

    Hello Lucas,
    I used Linux SDK 8.2 prebuilt binary on AM335x EVM in my test.
    As noted in my last reply.
    1/. The screenshot #1 is where I attached JTAG debugger, and paused u-boot running @u-boot prompt.
    2/. @u-boot prompt, I was able to modify CP15 SCTLR and ACTLR to disable L2 cache directly via JTAG debugger as shown in the screenshot #2.
    Best,
    -Hong