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OCTVO-3P-AM335X: VDDSHV Bump in Falling Waveform

Simon Acker
Prodigy 30 points
Part Number: OCTVO-3P-AM335X
Other Parts Discussed in Thread: TL5209

Good morning!

I am verifying a PCBA design with an Octavo OSD3358-512M-ICB C-SIP. This SOM contains a TPS65217C PMIC, TL5209 LDO, and an AM335x Sitara processor. LDO4 of the PMIC (a 3.3V LDO) powers VDDSHV 1, 3, 4, 5, and 6. VDDSHV 2 is powered by a 1.8V supply (LDO3). During the power down sequence, I'm seeing a little bump on the falling waveform of the supply that powers the five 3.3V VDDSHV pins. We have not satisfactorily tracked down the root cause of this behavior. That investigation is ongoing. In the meantime, I am hoping for clarity on whether this behavior is concerning? Will it damage the AM335x processor? Have you seen this behavior before? Thanks!

Pin legend: 

  • VDDSHV_3P3V -> TPS56217C LDO4
  • SYS_VDD1_3P3V -> TL5209 Output
  • VDD_CORE -> TPS56217C DCDC3
  • VDD_MPU -> TPS56217C DCDC2

Note: I confirmed that registers 0x19 - 0x1E of the TPS56217C match the reset states for the variant of the IC.

  • 0
    TI__Guru**** 189029 points

    Hello Simon Ackert

    Thank you for the query.

    Have you reached out to  Octavo  to check if they have some inputs?

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 30 points

    Hi Sreenivasa,

    Yes, I am separately inquiring with them. However, they cannot speak to the AM335x itself. Do you have any insight on the AM335x front?

    Thanks,

    Simon

  • 0 in reply to Simon Acker
    TI__Guru**** 189029 points

    Hello Simon Ackert

    Thank you. Could you please read the below, make the measurements and verify the sequence.

    6.1.2 Power-Down Sequencing
    PWRONRSTn input terminal should be taken low, which stops all internal clocks before power supplies
    are turned off. All other external clocks to the device should be shut off.
    The preferred way to sequence power down is to have all the power supplies ramped down sequentially in
    the exact reverse order of the power-up sequencing. In other words, the power supply that has been
    ramped up first should be the last one that should be ramped down. This ensures there would be no
    spurious current paths during the power-down sequence. The VDDS power supply must ramp down after
    all 3.3-V VDDSHVx [1-6] power supplies. If it is desired to ramp down VDDS and VDDSHVx [1-6] simultaneously,
    it should always be ensured that the difference between VDDS and VDDSHVx [1-6] during the entire power-down sequence is <2 V. Any
    violation of this could cause reliability risks for the device. TI recommends maintaining VDDS ≥1.5V as all
    the other supplies fully ramp down to minimize in-rush currents.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 30 points

    Hi Screenivasa,

    We have a clamping circuit that ensures VDDS and VDDSHx[1-6] remain within 2V throughout the power-down sequence. This bump does seem to be caused by a spurious current path, despite our design exhibiting the correct supply power down sequence. Does this bump concern you? Do you have any suggestions on potential current pathways inside the AM335x that could be causing the bump we're seeing? Thanks!

  • 0 in reply to Simon Acker
    TI__Guru**** 189029 points

    Hello Simon Acker

    Let me check and update.

    Do you have any IOs powered by any of the VDDSHVx set to 1,8V?

    Can you confirm these IO inputs are within the specified range.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 30 points

    Resolved. We had the Octavo connected to an ethernet switch via an RGMII connection. The ethernet switch remained powered when the Octavo was off. The powered ethernet switch continued to provide a clock waveform via the RX_CLK signal of the RGMII connection. This clock waveform was causing the bump discussed previously. It was also causing SYS_VDD3_3V3 and SYS_VDD1_3V3 to read non-zero voltages (1V & 0.5V, respectively) when the PMIC was off. 

    Thanks for your help Kallikuppa.

  • 0 in reply to Simon Acker
    TI__Guru**** 189029 points

    Hello Simon Acker

    Thank you for the inputs. This is appreciated and glad to support resolve the issue.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 189029 points

    Hello Simon Acker

    Please refer below additional inputs

    It is recommended to replace the processor on all boards that were exposed to this condition because the ESD protection circuits in the IOs may have been compromised and fail later.

    Regards,

    Sreenivasa