AM6442: Question related to Interrupt Aggregator schematic, detailed description, register set, and API

Before I answer your specific questions, I wanted to list a few things which help explain the interrupt aggregator and ELT and all the events:

1. Interrupt aggregator includes three orthogonal functions:
   1. one is event mapping block which converts local/umapped event to global event and send those events out.
   2. Second is aggregating global events and convert them into interrupt outputs
   3. Third is the L2G block:this is a block to convert the event/interrupt from SoC level into global events. L2G block takes wired signal from SoC  (interrupt signal or DMA signal) converted into local events.
2. L2G: this is a block to convert the event/interrupt from SoC level into global events. L2G block takes wired signal from SoC  (interrupt signal or DMA signal) converted into local events. Those local events are sent to ETL and sent to event mapping logic inside interrupt aggregator to convert them into global event. And then those global events are sent out again.
3. PSIL and ETL: PSIL is a streaming protocol which carries both data information and event information.  ETL is the PSIL portion which only carries event. PSIL data is transported independently. When you see PSIL, it must include ETL.
4. Local events and unmapped events are in the same category. All those unmapped/local events are  routed to  the mapping block inside Interrupt aggregator to be converted into global events
5. Other than L2G block, Currently there are only three components generating unmapped events: BCDMA, PktDMA and timer manager. All those unmapped events are routed to the event mapping block inside interrupt aggregator first. All the other components produce global events.
6. After the local/unmapped events are mapped to global events in interrupt aggregator, those global events are sent out by interrupt aggregator and can be transported to different locations ( for example, BCDMA to trigger BCDMA or pktDMA  or going back to interrupt aggregator’s aggregating global events into interrupts.

I draw a picture to demonstrate the concepts I described above: I do not know how to attach the picture to the response. I will ask my college for help.

For the more specific questions:

1. VINT registers that we have 184 of each register set.[Chunhua]:VINT registers means # of output interrupts. User can use  each VINT register set to determine which global events can be used to trigger this interrupt output.
2. IMAP registers. we have 1536 of these registers. They contain the register number and the bit number of VINT that caused the interrupt to happen. How is that possible? We have 184 VINT register set, each having 64 bits, meaning 11776 possibility. It doesn’t match with the value 1536. Are these events the same as SEVI that is mentioned in TRM?[ Chunhua]: 1536 means total global events. There are total 1536 total global events. You can route any of those 1536  events to any of the VINT register set to as interrupt cause for that interrupt output. For each interrupt output, you can define up to 64 possible global events to trigger this interrupt.
3. L2G registers. These registers contain level/edge and global event index. What is this global event index? Is it part of the 184 x 64 possibilities? Or part of the 1536 registers? Chunhua]:each local event needs to be mapped to a global event. Global event is identified with global event index. The global event index is unique.
4. We have some global event mapping registers. I think we have 256 of them for case of AM64x. What are these global events? If we consider the three categories defined earlier, does it fall into any of them? Chunhua]:This is for countable global events. But I see the register description may not be correct. I am checking with our IP designer to get more information. 
5. The same thing for multi-cast events mapping registers. Chunhua]:Please ask IP team. I am not familiar with the specific MMR usage.
6. The same thing for unmapped mapping registers. Chunhua]:the unmapped registers are the MMR to convert unmapped event into global event.

Before I answer your specific questions, I wanted to list a few things which help explain the interrupt aggregator and ELT and all the events:

1. Interrupt aggregator includes three orthogonal functions:
   1. one is event mapping block which converts local/umapped event to global event and send those events out.
   2. Second is aggregating global events and convert them into interrupt outputs
   3. Third is the L2G block:this is a block to convert the event/interrupt from SoC level into global events. L2G block takes wired signal from SoC  (interrupt signal or DMA signal) converted into local events.
2. L2G: this is a block to convert the event/interrupt from SoC level into global events. L2G block takes wired signal from SoC  (interrupt signal or DMA signal) converted into local events. Those local events are sent to ETL and sent to event mapping logic inside interrupt aggregator to convert them into global event. And then those global events are sent out again.
3. PSIL and ETL: PSIL is a streaming protocol which carries both data information and event information.  ETL is the PSIL portion which only carries event. PSIL data is transported independently. When you see PSIL, it must include ETL.
4. Local events and unmapped events are in the same category. All those unmapped/local events are  routed to  the mapping block inside Interrupt aggregator to be converted into global events
5. Other than L2G block, Currently there are only three components generating unmapped events: BCDMA, PktDMA and timer manager. All those unmapped events are routed to the event mapping block inside interrupt aggregator first. All the other components produce global events.
6. After the local/unmapped events are mapped to global events in interrupt aggregator, those global events are sent out by interrupt aggregator and can be transported to different locations ( for example, BCDMA to trigger BCDMA or pktDMA  or going back to interrupt aggregator’s aggregating global events into interrupts.

I draw a picture to demonstrate the concepts I described above:

 I am not able to attached the file here. I will aske my TI colleague to add it later.

For the more specific questions:

1. VINT registers that we have 184 of each register set.[Chunhua]:VINT registers means # of output interrupts. User can use  each VINT register set to determine which global events can be used to trigger this interrupt output.
2. IMAP registers. we have 1536 of these registers. They contain the register number and the bit number of VINT that caused the interrupt to happen. How is that possible? We have 184 VINT register set, each having 64 bits, meaning 11776 possibility. It doesn’t match with the value 1536. Are these events the same as SEVI that is mentioned in TRM?[ Chunhua]: 1536 means total global events. There are total 1536 total global events. You can route any of those 1536  events to any of the VINT register set to as interrupt cause for that interrupt output. For each interrupt output, you can define up to 64 possible global events to trigger this interrupt.
3. L2G registers. These registers contain level/edge and global event index. What is this global event index? Is it part of the 184 x 64 possibilities? Or part of the 1536 registers? Chunhua]:each local event needs to be mapped to a global event. Global event is identified with global event index. The global event index is unique.
4. We have some global event mapping registers. I think we have 256 of them for case of AM64x. What are these global events? If we consider the three categories defined earlier, does it fall into any of them? [Chunhua]:This is for countable global events. The register description does not look right. I am checking with our internal team to verify it. will follow up.
5. The same thing for multi-cast events mapping registers. [Chunhua]:Please ask IP team. I am not familiar with the specific MMR usage.
6. The same thing for unmapped mapping registers. [Chunhua]:the unmapped registers are the MMR to convert unmapped event into global event.

Hi,

Thanks for your detailed answer along with the schematics. It was very helpful

 
Can you please tell me what is the countable global events and what's the difference with the normal global events that you mentioned?

Chunhua Hu said:

:This is for countable global events.

In the meantime, I found a figure in the Errata file for AM243x which with your explanation makes it more clear. 

Would you please correct my understanding if it's wrong: 

The events that are unmapped/local (BCDMA, PKTDMA, Timer Manager) go to the unmapped module to make it to global events. It is done by unmapped register sets by assigning them a global index in addition to defining the type of interrupt (edge/level). This module generates global events. 

The Soc Events that are local (like GPIO, TimeSynch, etc) go to the L2G module and it converts them to global by assigning them a global index in addition to defining the type of interrupt (edge/level). This module generates global events. 

Global Events generated on the Unmapped Module or L2G module, as well as other events (that are inherently global), can go to the MultiCast Block to be used for triggering the BCDMA/PKTDMA  or to be sent to other modules that are connected to PSIL and can receive an event from that. 

Based on your explanation, I believe the module VINT Status Bits is the module that generates interrupts based on global events.

Chunhua Hu said:

r going back to interrupt aggregator’s aggregating global events into interrupts.

1. However, it is not clear to me what is the "Counted Event Block" and why there is a connection between MultiCast Block, Counted Event Block, and Status Event Block.
2. Does Counted Event Block really count the number of global events coming? Does it mean that when we split a global event into two, we need to count it two times one time going directly to this block and one time from Multicast to this block to count it two times?
3. If the above is correct, then why the output of all these three blocks are getting into the VINT Status Bits? In this case, we are sending the same global event three times to the VINT Status block. 

Thank you so much for your time. 

Boshra

There are some content missing from the TRM to explain the countable global events. I've already flag this to our internal team for the future TRM update.

Each countable global event has two MMR, one is GEVI[a].MAP and the second one is GEVI[a]_COUNT. The count register is self explanatory, which is tracking  # of event count for this global countable events. When one global event is generated with this event index, the event count is increased by one. When one of the end point consumes this global event with this index, the event count will be reduced by one. This operation is tracked by HW automatically.

The GEVI[a]_MAP register, the following explains the two modes it supports:

The countable global events generate either an event ( when irqmode is set to 0) or an interrupt ( when irqmode is set to 1) when the count of the events goes from zero to non-zero or from non-zero to zero. 

When irqmode is set to 0, the gevidx field is determine the global event index this event sent out to the system.

when irqmode is set to 1, the gevidx field is used to set the mapper register for the virtual interrupt. bit14:6 is used to determine which virtual interrupt this countable event sent to and  bit 5:0 is determine the bit fields of 64 possible bit for the virtual interrupt.

The below are the register definition for countable event for your reference. I hope it helps clarifying your question.

Regards,

Chunhua

1.1          MMR Region: intaggr_gcntcfg

The Global Event Count Registers CFG region is accessed by setting the cfg_rsel signal to 4 during the access.  The address map for this region is as follows:

1.1.1    Register Map

1.1.2    Register Definitions

1.1.2.1            GEVI[a]_MAP (Gobal Event Mapping Register), ((a*0x20)), a=0..255

The Global Event Mapping register controls the egress global event index for this event count. This register may also be optionally used to directly set an interrupt status bit by using the irqmode flag.

1.2          MMR Region: intaggr_gcntrti intaggr_gcntcfg

The Global Event Count Registers RTI region is accessed by setting the cfg_rsel signal to 6 during the access.  The address map for this region is as follows:

1.2.1    Register Map

1.2.2    Register Definitions

1.2.2.1            GEVI[a]_COUNT (ETL Count Register), ((a*0x1000)), a=0..255

The ETL Count register is read by software to determine how many times the event message has been received. This register can be written to decrement the count by a specified amount to acknowledge that a count has been processed by the host.