SPI2 EDMA conflict with video encode?

YJ Liu

hi guys:

My platform is DM365+DVSDK4.0.

I need to output video through SPI2, so I change the SPI driver( using EDMA) as slave device and modify the "encode" demo. But I found some interesting things.

1、I wrote some data transfer test program through SPI2 with EDMA, and it seems OK. We used a DSP as SPI host to read the data through DM365. When DM365 runs without video encode, the data transfer OK.

It was tested OK both under 10Mbps and 3Mbps SPI clock.

2、when I run the "encode" demo, and write the video data to SPI2 bus, the EDMA seems to be interrupted by others. For example, when I start SPI2's EDMA to transmit 4096 Bytes, the Host need to provide more than 4096byte clock, otherwise the EDMA may be stuck. It means when EDMA is transmitting data ,but interrupted by the video encode module, at the same time the SPI Host contineously provide clock and read data. At the end Host SPI stop but EDMA lost some clock to transmit other data and thus it is stuck.

When the spi clock is 10Mbps, the error happens frequently.

When using 3Mbps, the error become less.

So I think it's the problem of priority of EDMA or the DDR throughput .

What do you guys think ? could someone give some tips?

Thanks!

over 14 years ago

YJ Liu over 14 years ago

Expert 1675 points

Has Someone changed the priority of EDMA before? How?

Clemens Reisner over 14 years ago

Prodigy 80 points

Hi YJ Liu,

I got the same problem on a DM6467.

Did you found a solution for this?

Thanks!

Clemens Reisner over 14 years ago in reply to Clemens Reisner

Prodigy 80 points

Crosspost from other Thread: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/t/158350.aspx#576945

Maybe someone could help me with my problem on DM6467:

In my project I am using the danvici_spi linux kernel driver which uses DMA by default. I have an userspace application which receive encoded h264 video data from the DSP. This application puts the data via a ioctl() to kernel space. A self developed kernel module waits for IRQ signals from an external FPGA. If an IRQ was received it starts a spi transmission with 1024 bytes of video data. My SPI is operating at 24.75 MHz and transmission rate is about 8Mbit --> ~1 irq every ms. It takes about 500µs between the IRQ routine gets executed and the spi transmission is finished. The exact time deppends on the scheduling of the linux kernel. The ARM CPU usage in my project is jumping between 1% and 5% (kernel + userspace software).

There are still problems with the DMA transfers of the davinci_spi driver in my project. I have written a test application for my kernel module. This one transmites dummy data over SPI. In this case everything works perfect.

When i use my video-application in combination with the kernel spi transmission i get a lot of SPI transmission error (visible in kernel log, dmesg). After analyzing the davinci_spi kernel source it seems that a faulty DMA transfer cancels the SPI transmission. This error does occur sporadically. This faulty DMA transfers may be caused by the data transfer betweeen ARM and DSP during video encoding.

Maybe someone could give me a hint, how to fix the problem.

sriram garikipati over 13 years ago in reply to Clemens Reisner

Prodigy 220 points

Hi All,

Me too facing similar kind of issue, while writing to SPI-EEPROM in parallel to video encode task on DM6437 using BIOS.

I am using McBSP BIOS driver to to communicate with the SPI-EEPROM. I have tested writing to SPI-EEPROM with simple test code running in background. It works fine.

But when I am trying to do it in parallel to H.264 encoding then it fails. The h.264 encoder runs fine while the SPI eeprom write fails. I am writing the data to SPI -EEPROM in chunks of 256 bytes. SPI write fails after some n*256 bytes write. I tried to change the priority of the QDMA queue( qdmaQueueMap) using DMAN3_PARAMS structure. But the problem remains. Is it possible to change the priority of the DMA event of the SPI driver?? I am just suspecting the issue with DMA. but not confirmed.

I am driving SPI-EEPROM as slave with 300Khz clock while DM6437 running at 594Mhz.

can anybody please suggest how to deal with this bug.

regards,

Sri

Clemens Reisner over 13 years ago in reply to sriram garikipati

Prodigy 80 points

Hello,

I found following solution for my problem (see the above post)

I am using the Linux Kernel 2.6.32 from dvsdk. I have changed the EventQ for the spi controler. This value can be found in arch/arm/mach-davinci/dm6467.c

static struct resource dm646x_spi0_resources[] = {
{
  .start = 0x01c66800,
  .end   = 0x01c66fff,
  .flags = IORESOURCE_MEM,
},
{
  .start = IRQ_DM646X_SPINT0,
  .flags = IORESOURCE_IRQ,
},
{
  .start = 17,
  .flags = IORESOURCE_DMA,
},
{
  .start = 16,
  .flags = IORESOURCE_DMA,
},
{
  .start = EVENTQ_0,// <----------- CHANGE -------------EVENTQ_3,
  .flags = IORESOURCE_DMA,
},
};

You can try EVENTQ_0 to EVENTQ_3.

regards

sriram garikipati over 13 years ago in reply to Clemens Reisner

Prodigy 220 points

Hi clemens,

Thanks a lot for your prompt reply, I tried changing the priority of the DMA event queue but the problem remains. I checked for the stack overflow as well. All tasks stacks are fine.

Apart from the H.264 encoding and McBsp interrupt (Tx,Rx) ,systems uses PRD interrupts also. If I disable encoder task the system works fine. Also one more thing I observed

was in debug mode of the McBsp driver the issue was less frequent but when I use release mode of the driver the issue was very frequent. I am new to multitasking.. am I missing any basic thing..?

any ideas much appreciated.

many thanks

regards,

Sri

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SPI2 EDMA conflict with video encode?