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AM6411: R5 remoteproc configuration

Part Number: AM6411
Other Parts Discussed in Thread: AM6421, AM6422, AM6412

We're currently adjusting our TQMa64xxL SoM BSP for the AM6411 by removing or disabling cores and peripherals from the ti-linux 6.1 kernel's AM64x DTBs that do not exist on this SoC variant. This works fine for the most part, but we haven't been able to get the R5 remoteproc driver to work.

Besides disabling the second core of the first R5FSS and the whole second R5FSS, changes to the driver seem to be needed as well. As a test, I tried changing the Device Tree to use the configuration of the AM62x (change compatible to use am62_soc_data, update TCM sizes, remove ti,cluster-mode), but so far every attempt has either ended with ti_k3_r5_remoteproc failing to probe, or the whole system freezing during probe.

Can you tell us what changes are necessary to make the R5 work? Also, would the am64-main-r5f0_0-fw example from the ti-rtos-firmware package work on the AM6411 without changes?

Regards,
Matthias

  • Hello Matthias,

    Sorry for the delayed response since I was on leave last week.

    This question mostly belongs to Linux, and currently, Linux experts are not available.

    Now, we will follow the below steps; if they do not work out, then we will take help from Linux experts as well.

    Please look at the below FAQ, and it clearly explains how to enable cores based on custom core selection for IPC in MCU+SDK and the next-generated Multicore app image.

    The same things you have to do on the Linux side as well for customer core selection

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1220573/faq-am6442-faq-am64x-generating-an-ipc-multicore-app-image-for-a-custom-selection-of-cores

    Check below FAQ as well .

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1245326/faq-rpmsg-how-to-add-multiple-endpoints-to-a-remote-core-running-rtos

    Regards,

    S.Anil.

  • Hello Matthias,

    The information you are looking at is currently hiding in the next draft of the AM64x Academy, which will add a Multicore Academy alongside the AM64x Linux academy.

    Here is the AM62x version of the page you are looking for:
    https://dev.ti.com/tirex/explore/node?node=A__ARxKiGQnRRZIrn8bcmYQPw__linux_academy_am62x__XaWts8R__LATEST

    Here is additional information that will be added to the AM64x version of that page:

    Cores should be disabled if:

    * The processor silicon variation does not have those remote cores. For example,
    AM6422 & AM6421 have one R5F dual core subsystem instead of two subsystems,
    and AM6412 & AM6411 have one R5F subsystem with a single R5F core.

    * The application does not use the remote cores that are on the processor. Disabling
    a core allows us to free up system resources (like memory) for usage by other cores.

    ...........................................

    the warning about "device management subsystem R5F" does not apply to AM64x

    .........................................

    and then the section "Device tree changes to disable remote cores" changes like this:

    For example, let's say we are using AM6411, and we are not using the M4F
    core. In that case, we must also disable one of the R5F subsystems, and set
    the other R5F subsystem to single-CPU mode.

    and this is the AM64x patch file:

    From 3af2225a8c3f8863c40c5423396c373d20538d5a Mon Sep 17 00:00:00 2001
    From: Nick Saulnier <nsaulnier@ti.com>
    Date: Mon, 2 Oct 2023 16:02:45 -0500
    Subject: [PATCH] AM64x SDK 9.0: disable all cores but r5fss0_0
    
    These cores are set to "disabled":
    r5fss0_1, r5fss1_0, r5fss1_1, m4f
    
    The mailbox node settings can be deleted, since the mailbox is no longer
    being used for RPMsg communication between the disabled cores and Linux.
    
    The disabled cores' memory allocations in DDR are released for use by other
    parts of the processor system.
    
    Since there is now only one MCU+ core running (r5fss0_0), the
    rtos_ipc_memory_region is no longer used for IPC communication between MCU+
    cores. This memory region can also be removed.
    
    Signed-off-by: Nick Saulnier <nsaulnier@ti.com>
    ---
     arch/arm64/boot/dts/ti/k3-am642-sk.dts | 99 +++-----------------------
     1 file changed, 9 insertions(+), 90 deletions(-)
    
    diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
    index de0ff5af5e63..9cd48f35e2e7 100644
    --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
    +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
    @@ -50,60 +50,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
     			reg = <0x00 0xa0100000 0x00 0xf00000>;
     			no-map;
     		};
    -
    -		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
    -			compatible = "shared-dma-pool";
    -			reg = <0x00 0xa1000000 0x00 0x100000>;
    -			no-map;
    -		};
    -
    -		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
    -			compatible = "shared-dma-pool";
    -			reg = <0x00 0xa1100000 0x00 0xf00000>;
    -			no-map;
    -		};
    -
    -		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
    -			compatible = "shared-dma-pool";
    -			reg = <0x00 0xa2000000 0x00 0x100000>;
    -			no-map;
    -		};
    -
    -		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
    -			compatible = "shared-dma-pool";
    -			reg = <0x00 0xa2100000 0x00 0xf00000>;
    -			no-map;
    -		};
    -
    -		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
    -			compatible = "shared-dma-pool";
    -			reg = <0x00 0xa3000000 0x00 0x100000>;
    -			no-map;
    -		};
    -
    -		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
    -			compatible = "shared-dma-pool";
    -			reg = <0x00 0xa3100000 0x00 0xf00000>;
    -			no-map;
    -		};
    -
    -		mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
    -			compatible = "shared-dma-pool";
    -			reg = <0x00 0xa4000000 0x00 0x100000>;
    -			no-map;
    -		};
    -
    -		mcu_m4fss_memory_region: m4f-memory@a4100000 {
    -			compatible = "shared-dma-pool";
    -			reg = <0x00 0xa4100000 0x00 0xf00000>;
    -			no-map;
    -		};
    -
    -		rtos_ipc_memory_region: ipc-memories@a5000000 {
    -			reg = <0x00 0xa5000000 0x00 0x00800000>;
    -			alignment = <0x1000>;
    -			no-map;
    -		};
     	};
     
     	vusb_main: fixed-regulator-vusb-main5v0 {
    @@ -556,44 +502,25 @@ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
     		ti,mbox-rx = <0 0 2>;
     		ti,mbox-tx = <1 0 2>;
     	};
    -
    -	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
    -		ti,mbox-rx = <2 0 2>;
    -		ti,mbox-tx = <3 0 2>;
    -	};
     };
     
     &mailbox0_cluster3 {
     	status = "disabled";
     };
     
    -&mailbox0_cluster4 {
    -	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
    -		ti,mbox-rx = <0 0 2>;
    -		ti,mbox-tx = <1 0 2>;
    -	};
    -
    -	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
    -		ti,mbox-rx = <2 0 2>;
    -		ti,mbox-tx = <3 0 2>;
    -	};
    -};
    -
     &mailbox0_cluster5 {
     	status = "disabled";
     };
     
    -&mailbox0_cluster6 {
    -	mbox_m4_0: mbox-m4-0 {
    -		ti,mbox-rx = <0 0 2>;
    -		ti,mbox-tx = <1 0 2>;
    -	};
    -};
    -
     &mailbox0_cluster7 {
     	status = "disabled";
     };
     
    +/* set R5F subsystem to single-CPU mode */
    +&main_r5fss0 {
    +	ti,cluster-mode = <2>;
    +};
    +
     &main_r5fss0_core0 {
     	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
     	memory-region = <&main_r5fss0_core0_dma_memory_region>,
    @@ -601,27 +528,19 @@ &main_r5fss0_core0 {
     };
     
     &main_r5fss0_core1 {
    -	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
    -	memory-region = <&main_r5fss0_core1_dma_memory_region>,
    -			<&main_r5fss0_core1_memory_region>;
    +	status = "disabled";
     };
     
     &main_r5fss1_core0 {
    -	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
    -	memory-region = <&main_r5fss1_core0_dma_memory_region>,
    -			<&main_r5fss1_core0_memory_region>;
    +	status = "disabled";
     };
     
     &main_r5fss1_core1 {
    -	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
    -	memory-region = <&main_r5fss1_core1_dma_memory_region>,
    -			<&main_r5fss1_core1_memory_region>;
    +	status = "disabled";
     };
     
     &mcu_m4fss {
    -	mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
    -	memory-region = <&mcu_m4fss_dma_memory_region>,
    -			<&mcu_m4fss_memory_region>;
    +	status = "disabled";
     };
     
     &ecap0 {
    -- 
    2.34.1
    

    Regards,

    Nick

  • Feel free to poke around the other pages added in the Multicore academy, there is other information that might be interesting for you.

    e.g., if the firmware is being loaded by Linux remoteproc driver, you should check out section
    "how to create remote core firmware that can be loaded by Linux:"
    https://dev.ti.com/tirex/explore/node?node=A__AVP4Q-S9hfvfv8aDiSbBJw__linux_academy_am62x__XaWts8R__LATEST

    Regards,

    Nick

  • Hi Nick,

    thank you for your reply - I finally got around to try it out. Your patch is fairly similar to the changes I attempted to make myself before I opened this thread. Unfortunately, the changes are not sufficient to make the Remoteproc driver work (on current ti-linux-kernel 6.1):

    • The ti_k3_r5_remoteproc has a consistency check that will fail with "MCU cluster requires both R5F cores to be enabled but num_cores is set to = 1" when I modify the Device Tree as suggested
    • When I comment out that check, the whole system will hang after printing "platform 78000000.r5f: configured R5F for remoteproc mode"

    Regards,
    Matthias

  • Hello Matthias,

    Apologies for the delayed response, I lost your thread over Thanksgiving. I will try to replicate your results on Friday. Please ping the thread if I have not responded by Monday.

    Regards,

    Nick

  • Helli Matthias,

    It turns out that you are not supposed to disable core1 of the R5F subsystem that is being set to single-core mode.

    Future readers, I have already pushed the latest (working) patch to the AM64x Academy - it should show up within the next day or so. Starting in AM64x Academy 9.00.00.00 v2, reference Multicore module, page "Booting and disabling processor cores"
    https://dev.ti.com/tirex/explore/node?a=7qm9DIS__LATEST&node=A__ATo1YYblar8bnpnjYwvd1g__AM64-ACADEMY__WI1KRXP__LATEST 

    I'll also attach the updated patch here:

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/8726.0001_2D00_AM64x_2D00_SDK_2D00_9.0_2D00_disable_2D00_all_2D00_cores_2D00_but_2D00_r5fss0_5F00_0.patch

    Regards,

    Nick

  • Hi Nick,

    thanks for the new patch, the AM6411 R5 is working nicely now - I was able to boot the IPC example and run the rpmsg_client_sample test with the changes applied.

    Regards,
    Matthias

  • Thanks for confirming Mattias! Please feel free to create a new thread if you have any other questions or feedback.

    Regards,

    Nick