Part Number: TDA4VM
Hello Experts,
I am using UDMA to transmit and receive data over UART using own UART driver and TI UDMA driver.
I observed that when force teardown(timeout = 0ms) is requested while transmission of data is ongoing, the PEER8 register values is 0x10000002. This means FLUSH bit is 1.
My teardown call sequence is as follows.
/* Disable Cq event. */
if(UDMA_SOK == ret) ret = Udma_eventDisable((Udma_EventHandle) &ch->udmaCqEventObj);
/* Force teardown. Timeout is 0ms. */
if(UDMA_SOK == ret) ret = Udma_chDisable((Udma_ChHandle)&ch->udmaChObj,0u);
if(UDMA_SOK == ret) ret = Udma_ringDequeueRaw(Udma_chGetCqRingHandle((Udma_ChHandle)&ch->udmaChObj), &pDesc);
if(UDMA_SOK == ret) ret = Udma_chDequeueTdResponse(&ch->udmaChObj,&tmp);
When i want to enable the channel again to transmit, FLUSH bit stays 1 (PEER8 = 0x90000000 )and then I do not see any output in the UART bus.
As per TI documentation,
When set, causes all TX channel data to be discarded instead of
being written to the peripheral. It essentially allows the TX engine to
'free run' without DMA requests from the peripheral (it will also
override 'pause'). This bit should be set only when a channel fails to
complete its teardown procedure normally because a peripheral is no
longer functioning or because data flow was halted on a boundary
that is not compatible with the static TR configuration.
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Question:
1. How FLUSH bit shall be cleared when force teardown is requested previously? Will this be cleared by SW or HW?
2. As per TI document, force teardown is termed as "catastropic". What needs to be done after such force teardown to ensure the UDMA works normally?
Thanks
Nazim
