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How to interface C6678 with FPGA?

Lee Lemay
Prodigy 110 points

Hi folks,

I'm looking to connect a C6678 with a Xilinx Spartan 6.

The three main options appear to be:

  • EMIF16  (several schemes are available to allow the FPGA to be accessed this way.)
  • SRIO      (FPGA ip for SRIO is available to be purchased from Xilinx.)
  • PCIe       (1 lane of PCIe v1.1 is available on the Spartan 6.)

SRIO is a non-starter because Xilinx is charging for its SRIO ip core.

PCIe would work, but I would like to save that interface for a connector. If the board has space I'll place a PCIe switch, and then I can connect the DSP with the FPGA using PCIe. But I won't plan on that for now.

EMIF16 is my preferred option. What bandwidth can I achieve with it? It's clock is CPU/6, and its 2 bytes wide - for 1.25 GHz, does that mean I can achieve 416MB/s, or is there overhead I am not considering?

There was some talk in this thread of releasing FPGA ip to connect an FPGA with HyperLink (it's also mentioned in the C6678 data manual.) This would be ideal - it would certainly trump EMIF16.

This might be silly, but would it be possible to use SGMII? I haven't researched that interface at all, and its probably impossible, but I thought I'd ask.

I'd appreciate any suggestions and advice. Thanks for your help!

  • 0
    Expert 1120 points

    SGMII can be used for chip-to-chip interconnect. You can connect the SGMII interface of  C6678 to the SERDES/LVDS based tranceiver of FPGA. Since Spartan-6 FPGA does not have a hard ethernet mac block, you may want to use a soft IP -- fortunately, you can find a free IP from Xilinx. I suggest you to use raw ethernet data instead of TCP/IP stack if you do so.

    Implementing SRIO protocol in FPGA is not an easy job, and will cost you a lot if you buy one.

    If you chose EMIF, you could also connect SRIO or SGMII for design flexibility, after all these serial connections occupy not much space of you board.

    If you do not use any of the SERDES based interfaces, you could use a Spartan-6 LX FPGA that would save you a lot.

    This article might be helpful if you want to make a comparison among these high speed interfaces.

    Han

     

    6378.understanding srio pcie ethnet.pdf 

  • 0 in reply to haopeng han
    TI__Mastermind 46460 points

    Lee,

    What is the schedule for your board design?  We are working with the FPGA vendors to implement HyperLink for just this kind of application.  However, this has been delayed and I do not know when it will be available.

    What is your throughput requirement?  We recommend that you consider both short and long term.  This may limit your options.

    EMIF16 can be used with the FPGA for data transfer but it was not designed as a high-throughput interface.    The EMIF16 User Guide shows the read and write waveforms.  The duration of these waveforms is fully programmable to support slow memory devices.  It appears that the shortest cycle would be 3 clocks.  Assuming the DSP core clock is 1.25GHz, the EMIF16 transfer rate would be about 69.4MT/s for a throughput of 138.8MB/s.  This throughput will be lower when using multiple EMIF chip selects and when interleaving reads and writes.  Usable throughput is probably closer to 100MB/s.

    SGMII is a simple IP that is generally available.  It will provide this sustained throughput in both directions through a much lower pin-count.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 110 points

    Hi Tom and Haopeng,

    Thanks for your replies - they're very helpful.

    I'll plan on routing the hyperlink to the FPGA, and when/if the IP becomes available we can add it to the FPGA build.

    In the meanwhile I'll investigate SGMII and make sure it will get the job done. There are 2 SGMII ports on the C6678, so I can use one for Ethernet, and one for chip-to-chip interconnect, right?

    The minimum bandwidth for my application is 200 MB/s, so the EMIF16 will not get the job done. I'll plan on routing it and the SRIO to the FPGA anyway, for flexibility.

    Worst case, I can use PCIe.

    Thanks again for your help, and let me know if there is anything I'm missing.

  • 0 in reply to Lee Lemay
    TI__Mastermind 46460 points

    Lee,

    Is the throughput requirement of 200MB/s in one direction or both directions?  If both, then SG MII will not be sufficient.  If it is half in each direction, then SGMII will meet the minimum requirement without much margin and even then the packets must be large to keep the overhead from consuming too much bandwidth.

    The SGMII ports can be used independently without a problem.

    Tom