TDA4VM: [SDK 8.5][DSI] How to config CLK_P / CLK_N of the DSI signal?

Capture clock signal of DSI (CLK_P and CLK_N) It seems like they are noise signals.

Hi,

Due to a holiday, Our expert is on vacation kindly expect a 1~2 day delay in responses.

Best Regards,
Sudheer

Hi,

Please note that this is a differential signal, so it may not look like a clock signal.

What's the lane speed that you are setting? Is the DSS enabled? Because only after DSS is enabled, DSI will have some output.

Regards,

Brijesh

Hello Brijesh,

We're using 4 DSI lanes, DSI output solution is 1280*800 pixels in 25fps => lane rate is 153Mbps/lane.

We're config Display type is DSI and DSS was init done !

Best Regards,

Brown

Hi Brown,

No i meant to say, what is the value of parameter laneSpeedInKbps in Dss_DctrlDsiParams that you are setting?

Regards,

Brijesh 

Hello Brijesh,

following the log bellow, "laneSpeedInKbps" was set in 2.7Gbps

Best Regards,

Brown

Hi Brown,

ok, but i did not get what exactly issue you are facing? Is your DSI receiver not able to detect the input signal? or something else? Why do you require to probe the signal? 

Regards,

Brijesh

Hello Brijesh,

Our system model as I shown above. We set video signal output via DSI (Pic_1) and Data lane we captured seem that they already have data signal output. However, our system couldn't output any video yet. We captured CLK_P/CLK_N pins and found that there are no any clock signal.

Questions is: Lacking CLK_P/CLK_N caused missing video data output, didn't it ?

If yes, how can we configuration CLK_P/CLK_N signal ?

Best Regards,

Brown

Hi Brown,

That's strange. Data lane cannot have data without clock on the clock lane. Are you sure that you are seeing some data on the data lanes? 

Also is your receiver detecting some valid clock and data signals? 

Regards,

Brijesh

Hello Brijesh,

Pictures below are wave form of DATA lane of DSI before and after execute Vision_Apps. In the second picture (after execute visions_apps), there are look like data were transferred, aren't it ?

Before execute vision_apps:

After execute vision_apps:

CLK_P & CLK_N:

With wave forms of CLK captured above. They don't look like clock wave. So, the question is why when we set DSI enable by default, CLK wave are lacked ? Are we missing any steps in the configurate DSI? Where we could check/config it in the source code?

Thank You & Best Regards !

Brown

Hi Brown,

That's strange. Usually, clock is enabled in the continuous mode, so even when vision apps usecase is not started, there should be some clock on the clock lane.  Are you sure that this is probed on the clock lane and this clock is detected correctly on the receiver side? 

Regards,

Brijesh 

Hello Brijesh,

Thanks for your suggestion. We're sure that we have checked on CLK lanes correctly.

"Usually, clock is enabled in the continuous mode, so even when vision apps usecase is not started, there should be some clock on the clock lane."

==> So, that means, there usually exists clock signal on CLK lanes whenever the system is booted up whether vision_apps are executed or not. Isn't it?

==> Where could we configure CLK mode (enable/disable/continuous/non-continuous, etc)?

Thank You and Sincerely !

Brown

Dear Brijesh,

Sorry for late repy.

In "ti-processor-sdk-rtos-j721e-evm-08_06_00_12\pdk_jacinto_08_06_00_31\packages\ti\drv\dss\src\drv\dctrl\dss_dctrlDsi.c" I changed DSI parameter as below to enable 4 lanes. However, after modified, there are not have any data (signals) on any lane. Did I missed/wrong any steps?

Thank You and Best Regards,

Brown

Hi Brown,

With the same parameters, is the 2-lane output working fine? Can you please check it?

Regards,

Brijesh

Also i would suggest using driver interfaces for calculating these parameters. Based on input parameter laneSpeedInKbps, driver internally calculates these parameters by calling SET_DSI_PARAM ioctl.

Regards,

Brijesh

Hello Brijesh,

When config 2 lanes output as default, output are working fine. Lane signals as pictures above comments.

Best Regards,

Brown

ok, then with 2 lanes mode, what's the issue? Is your serializer or receiving device able to detect the incoming signal? 

Regards,

Brijesh

Good afternoon Brijesh,

The issue is in 2-lanes mode, CLK_P and CLK_N did not exist any signals as I mentioned above on the first of this topic.

Thank You and have a nice weekend !

Brown