Hi,
I'm working on DMSS on the AM64X HS-FS board.
I have some questions. All the references to TRM are either to AM64x/243x version 2.0 TRM or to AM65x TRM.
The following picture that I have drawn is my understanding of how the DMSS module works.
I would appreciate it if you could correct me if I'm wrong in describing it.
1.IA trigger can come from L2G to INTAGGR (like from GPIO through GPIO_INTRMUX), it will be mapped to PSI-L then it will go to the BCDMA module to do trigger the start of the transfer for BCDMA.
However, also there is a Ring pending coming from the Ring Accelerator to BCDMA (section 11.1.4.16, step 3, or figure 11-180). This signal is happening when there is an element queued in the ring waiting for transmission.
In the TRM the “Ring pending signal” is mentioned as “level sensitive status signal” in “This level sensitive status line is sent to the hardware block which is responsible for scheduling DMA operations”)
Finally, which of these two (Mapped trigger coming from PSI-L versus Ring Pending signal) triggers the start of transmission on BCDMA? Does it mean that it should be queued first and then triggered, or first the BCDMA should be triggered and then queued after?
The ring Pending concept is at section 10.1.3.8 of AM65x TRM, step 3, however in the AM64x TRM the word Ring Accelerator is replaced by BCDMA, which is very confusing.
2.In the AM64x TRM section 11.1.1.5.1.4, it is mentioned that the DMA controller (DMA read/write unit in case of BCDMA) initiates the VBUSM transfer to read descriptor pointers from memory-mapped rings, read descriptors, transfer request records and payload data from memory and keep it in the channel buffers in the meantime to transfer it to destination finally. It implements all the state machines required to perform these transfers. What does it mean here when it says "it initiates the VBUSM transfers"? Does it really send a read/write command on the VBUSM or not? The connection between VBUSM, BCDMA, and RA is not clear here.
In AM64x TRM there are two different types of figures that demonstrate the DMASS connections to the bus which makes it even more confusing:
a)This figure shows the only way the DMASS is connected to CBASS is either through the RA or through the SEC_PROXY. This Idea matches with the interconnect tables for CBASS; tables 3-7 and 3-10 show that the only connection to DMASS is either through SEC_PROXY or RING. However, in Table 3-10, we can see other DMASS connections on CBASS that are used for setting the register for DMASS as well (I believe these are not related to DMA data transfers)
b)In the following schematics, however, we see something different. We see that BCDMA and PKTDMA also have a connection to CBASS. Why there is a difference between the above figure/table and the following figures? It does not seem these connections are for the configuration of the registers, because the configurations are already shown with P_SLV. Therefore, what is this difference and why?
3.Based on my understanding the steps for a BCDMA-BlkCpy transfer are as follows. However, I’m not sure about step (f) as it is not clear in the TRM and I can interpret it in two different ways as I described in the following. Also as mentioned in item (2) the mismatching block-diagram figures do not help either.
In addition to that, the following figure from AM65x TRM gives me a second interpretation:
- First Interpretation:
- The software queues the Transfer Request Descriptor pointer into the proper ring (corresponding ring for the chosen channel for blkCpy operation).
- When the pointer is queued, RA sends a level status signal to the hardware block that is responsible for scheduling DMA (I believe in this case is the BCDMA Write/Read unit module).
- The BCDMA-BlkCpy channel will be triggered by a mapped event coming from IA.
- Receiving the trigger, the DMA controller is going to start to process the Transfer packet descriptor. Is it the case or still the channel still need to wait for the arbitration and its turn or it will escape its turn because it was triggered?
- DMA controller reads the packet descriptor pointer from the RA through the DMSS-CBASS.
- Then DMA controller reads the packet descriptor from the memory meaning that BCDMA reads the memory through CBASS (VBUSM).
- As TRs are read from the descriptor they are stored in the internal state of the DMA channel, until all are read.
- All the data transfers that are specified in the TR will be complete, meaning that the data payload transfers are happening from the internal BCDMA channel to the destination memory address through the CBASS (VBUSM).
- As each TR is completed and the response received, the response will be written into the Transfer Response record array, using CBASS (VBUSM) from BCDMA to the memory.
- When all the transfer requests in the packet are processed all the transfer responses received, and confirmed that they are landed in the memory, BCDMA writes the pointer to the descriptor in the return queue of the packet descriptor, meaning that BCDMA will write into the corresponding ring in the Ring Accelerator.
- Then RA sends an event for ring completion to the IA. However, if the event is based on the TR, I believe it will be triggered after transferring the defined number of bytes at step (h).
- The other interpretation is as follows:
a-e. The same
f. The RA translates it to the address for the proper ring pointer (based on the Ring Accelerator functional description in section 11.2.2.3 of the TRM). Then RA sends the command on CBASS to the memory to read the corresponding address and then passes the read packet descriptor to the BCDMA.
h-k. The same
- when in the TRM it talks about the channelized firewalls is it talking about the following? or is it sth else?
