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SK-AM62: 4G DDR on AM6234 does not function properly

Peter Liu
Prodigy 240 points
Part Number: SK-AM62
Other Parts Discussed in Thread: SYSCONFIG

Hello TI team,

I am currently using our own PCB board, MPU model AM6234ATCGGAALW, DDR model MT40A2G16TBB-062E:F, which includes BG0 and BG1 signal pins. We used AM62x-DDRConfig_MT40A2G16.gel files containing BG0 and BG1 pins to debug DDR and found that DDR still cannot be accessed normally. By using a AM62x-DDRConfig_MT40A2G16_BG0_only.gel file that only contains BG0 pins, DDR can be accessed normally. Could you please analyze the reason? Thank you!

The schematic diagram of the custom board DDR section is as follows:

The logs that failed to access DDR using DDRConfig_MT40A2G16.gel files are as follows:

/cfs-file/__key/communityserver-discussions-components-files/791/20231013_2D00_am62x_5F00_ddr_5F00_init_5F00_log.txt

 

/cfs-file/__key/communityserver-discussions-components-files/791/20231023_2D00_AM62_5F00_DDRSS_5F00_CTL_5F00_PI_5F00_PHY-.txt

This is the file generated by sysconfig,Using two BG signals simultaneously and changing the density to 32Gb:

/cfs-file/__key/communityserver-discussions-components-files/791/3201.all.zip

  • 0
    Prodigy 240 points

    I tried changing Density (per device) (Gb) to 16Gb, and then simulated using CCS. I found that the address ranges of 0x80000000-0x100000000 and 0x880000000-0x90000000 can be accessed normally, and when accessing 0x88000000, the content of the 0x8000000 address will not be overwritten.

    1.Can the density of the MT40A2G16TBB-062E:F model only be configured to 16Gb for normal operation?

  • 0 in reply to Peter Liu
    TI__Guru* 86180 points

    Peter, yes, this is the correct configuration.  Your "twin-die" device is technically 2 16Gb devices inside the same package, so the tool should be configured for 16Gb per device

    It sounds like you can successfully access all 4GB of the memory.  Correct?

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 240 points

    Hi James,

    I can now access 4GB of DDR correctly.

  • 0 in reply to Peter Liu
    TI__Guru* 86180 points

    Excellent!  Thank you for your patience in this issue.

    Regards,

    James

  • 0 in reply to JJD
    TI__Expert 4160 points

    Peter, 

    Have you brought up your Linux system with 4GB memory access correctly in Kernel and root file system?

    BR, Rich

  • 0 in reply to Peter Liu
    TI__Expert 4160 points

    Peter, 

    We are using same DDR model and applied same patches from JJD but having problem while using upper 2GB range in Kernel.

    May I know which Linux SDK version do you use? 

    Could you provide diff for the modifications you have done on SDK? 

    BR, Rich

  • 0 in reply to Rich Chen
    Prodigy 240 points

    Hi,

    The SDK version I am using is ti-processor-sdk-linux-am62xx-evm-08.06.00.42-Linux-x86-Install.

    uboot

    diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 0a4bf0c307..73d52f241d 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -737,8 +737,10 @@ static int k3_ddrss_probe(struct udevice *dev)
 		return ret;
 
 #ifdef CONFIG_K3_AM64_DDRSS
-	writel(0x000001EF, AM64_DDRSS_SS_BASE + 0x020); //VBUSM2AXI Control Register sdram_idx, region_idx 0x11 --> 0x0F = log2(connected SDRAM size) - 16
-	writel(0x0, AM64_DDRSS_SS_BASE + 0x120); //ECC Control Register 0x120 ecc_en = 0, rmw_en = 0, wr_alloc = 0, ecc_ck=0
+	// writel(0x000001EF, AM64_DDRSS_SS_BASE + 0x020); //VBUSM2AXI Control Register sdram_idx, region_idx 0x11 --> 0x0F = log2(connected SDRAM size) - 16
+	// writel(0x0, AM64_DDRSS_SS_BASE + 0x120); //ECC Control Register 0x120 ecc_en = 0, rmw_en = 0, wr_alloc = 0, ecc_ck=0
+	writel( ((readl(AM64_DDRSS_SS_BASE + 0x020) & ~0x3FF) | 0x210), AM64_DDRSS_SS_BASE + 0x020);
+	writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
 #endif
 
 	ddrss->driverdt = lpddr4_getinstance();
 	
diff --git a/arch/arm/dts/k3-am62x-r5-sk-common.dtsi b/arch/arm/dts/k3-am62x-r5-sk-common.dtsi
index b4a5e3cfa1..833231074e 100644
--- a/arch/arm/dts/k3-am62x-r5-sk-common.dtsi
+++ b/arch/arm/dts/k3-am62x-r5-sk-common.dtsi
@@ -19,8 +19,9 @@
 
 	memory@80000000 {
 		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+		/* 4G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
 
 		u-boot,dm-spl;
 	};
diff --git a/arch/arm/dts/k3-am62x-sk-common.dtsi b/arch/arm/dts/k3-am62x-sk-common.dtsi
index 72ebb1400f..8ce08592f5 100644
--- a/arch/arm/dts/k3-am62x-sk-common.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-common.dtsi
@@ -31,8 +31,9 @@
 
 	memory@80000000 {
 		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+		/* 4G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+		      <0x00000008 0x80000000 0x00000000 0x80000000>;
 
 	};
 
diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
index d92e3ce048..240584cc83 100644
--- a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
@@ -1,18 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60
- * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time)
+ * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.09
+ * Wed Oct 25 2023 11:04:28 GMT+0800 (中国标准时间)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
  * Number of Ranks: 1
- */
+*/
 
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
 
+
 #define DDRSS_CTL_0_DATA 0x00000A00
 #define DDRSS_CTL_1_DATA 0x00000000
 #define DDRSS_CTL_2_DATA 0x00000000
@@ -329,19 +330,19 @@
 #define DDRSS_CTL_313_DATA 0x00000000
 #define DDRSS_CTL_314_DATA 0x00000000
 #define DDRSS_CTL_315_DATA 0x00000100
-#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_316_DATA 0x00000000
 #define DDRSS_CTL_317_DATA 0x00000000
-#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_318_DATA 0x7FFF0000
 #define DDRSS_CTL_319_DATA 0x000FFF00
 #define DDRSS_CTL_320_DATA 0xFFFFFFFF
-#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_321_DATA 0x00FFFF00
 #define DDRSS_CTL_322_DATA 0x0A000000
 #define DDRSS_CTL_323_DATA 0x0001FFFF
 #define DDRSS_CTL_324_DATA 0x01010101
 #define DDRSS_CTL_325_DATA 0x01010101
 #define DDRSS_CTL_326_DATA 0x00000118
-#define DDRSS_CTL_327_DATA 0x00000C01
-#define DDRSS_CTL_328_DATA 0x00000000
+#define DDRSS_CTL_327_DATA 0x01000C01
+#define DDRSS_CTL_328_DATA 0x00000001
 #define DDRSS_CTL_329_DATA 0x00000000
 #define DDRSS_CTL_330_DATA 0x00000000
 #define DDRSS_CTL_331_DATA 0x01000000
@@ -513,7 +514,7 @@
 #define DDRSS_PI_74_DATA 0x00000000
 #define DDRSS_PI_75_DATA 0x00000005
 #define DDRSS_PI_76_DATA 0x01000000
-#define DDRSS_PI_77_DATA 0x04000100
+#define DDRSS_PI_77_DATA 0x04000000
 #define DDRSS_PI_78_DATA 0x00020000
 #define DDRSS_PI_79_DATA 0x00010002
 #define DDRSS_PI_80_DATA 0x00000001
@@ -901,7 +902,7 @@
 #define DDRSS_PHY_117_DATA 0x00800080
 #define DDRSS_PHY_118_DATA 0x00800080
 #define DDRSS_PHY_119_DATA 0x01000080
-#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_120_DATA 0x01000000
 #define DDRSS_PHY_121_DATA 0x00000000
 #define DDRSS_PHY_122_DATA 0x00000000
 #define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1158,7 @@
 #define DDRSS_PHY_373_DATA 0x00800080
 #define DDRSS_PHY_374_DATA 0x00800080
 #define DDRSS_PHY_375_DATA 0x01000080
-#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_376_DATA 0x01000000
 #define DDRSS_PHY_377_DATA 0x00000000
 #define DDRSS_PHY_378_DATA 0x00000000
 #define DDRSS_PHY_379_DATA 0x00080200
@@ -2152,7 +2153,7 @@
 #define DDRSS_PHY_1368_DATA 0x00000002
 #define DDRSS_PHY_1369_DATA 0x00000100
 #define DDRSS_PHY_1370_DATA 0x00000000
-#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
 #define DDRSS_PHY_1372_DATA 0x00020002
 #define DDRSS_PHY_1373_DATA 0x00000000
 #define DDRSS_PHY_1374_DATA 0x00001142

    kernel

    diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
index 3e7204440f..59ff3377ad 100644
--- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
@@ -8,25 +8,32 @@
 	memory@80000000 {
 		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+	/* 4G RAM */
+	reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+	<0x00000008 0x80000000 0x00000000 0x80000000>;
 
 	};

  • 0 in reply to Peter Liu
    TI__Expert 4160 points

    Peter, 

    Really appreciate for the sharing.

    It helps for our debug as a successful case reference. 

    I found all of changes are applied except the DDR timing could be different so we will take the same parameter you use here to see if we can get through it. 

    BR, Rich 

  • 0 in reply to Rich Chen
    TI__Expert 4160 points

    Peter, 

    May I ask a favor from you to share your SD image (mainly u-boot) for testing?

    My case here with 4GB DDR4 can operate normally with 2GB configuration but it will fail to boot in u-boot with 4GB configuration.

    We have spent too much time on this case without progress. 

    BR, Rich