Hi, all
I have a question on SDRC_MDCFG configure in x-loader:
In file include/asm/arch-omap3/mem.h #define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) /* Infin ddr module */.
According to DM/AM37x TRM, it means 13bits RAS width, 10 bits CAS width.
But in the LPDDR datasheet 7774.nandflash_mddr_pop_am37x_evm.pdf, it said, Row Address A0~A13, that is 14bits width, Column Address:A0~A9, that is 10 bits widhth, Auto-precharge flag is A10.
So the RAS width is not compatible in x-loader configure and mddr's spec.
Could you help to give some explanation for this?
Thanks!
Yaoming