TDA4VM-Q1: TDA4VM Boot issue from OSPI NOR Flash

Arumugam Elumalai

Part Number: TDA4VM-Q1
Other Parts Discussed in Thread: TDA4VM

Hello,

We are using the TDA4VM SOC in our design . The Boot configuration is set it as OSPI boot. The Boot flash device part# MT35XU02GCBA1G12-0AUT. While the module is powered ON, all the TDA SOC power supply voltages are generated from PMIC. The PMIC is able to release the reset signal as per the below drawing.

TI shared two flash file and flashed the file as per the below recommended location.

After loading the 2 files (not sure its flashed properly). But we verified the data stored in the device against the file and it seems to be fine. However, after loading the files, the UART log is below.

Is there anything that I need to look on to the Hardware to ensure everything is good for processor boot. And also, what could be the reason for this log.

Looking for your help in this regard.

Thanks-Arumugam

over 1 year ago

0 Parth Nagpal over 1 year ago

TI__Mastermind 42135 points

Hi,

Before moving to boot from OSPI, did you validate the OSPI interface with some example applications?
Do you have any other boot mode available? Can you try running OSPI driver example

Regards,
Parth

0 Arumugam Elumalai over 1 year ago in reply to Parth Nagpal

Intellectual 365 points

Hi, we put the SOC in no boot option and then tried to connect to JTAG emulator. But unfortunately, the EMU status not available msg received from UART debugger. Now we are trying to put the SOC in UART boot mode. Can you relate the EMU fault status with processor not boot in OSPI mode.

We are able to flash the NOR flash device using our NOR flash programmer.

0 Karan Saxena over 1 year ago in reply to Arumugam Elumalai

TI__Guru* 77854 points

Please share the delta patch on the SBL, there is an issue with the SBL configuration for the flash and hence the Board_flashOpen() is failing, leading to a failure in loading TIFS (or Sysfw).

Regards

Karan

0 Daviel Almonte over 1 year ago in reply to Karan Saxena

TI__Expert 3285 points

Here is the SBL src code we used. There were no modification on this file. instead we have modified the m35xu512.h with the updated manufacture ID as ZF is using the same family of device but with a larger density and it has four die stack. as well as the DDR reg that was generated from the DDR config tool.

SBL:

/**
 *  \file    sbl_ospi.c
 *
 *  \brief   This file contains functions for OSPI read/write operations for SBL
 *
 */

/*
 * Copyright (C) 2018-2022 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the
 * distribution.
 *
 * Neither the name of Texas Instruments Incorporated nor the names of
 * its contributors may be used to endorse or promote products derived
 * from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include <stdint.h>
#include "string.h"

/* SBL Header files. */
#include "sbl_soc.h"
#include "sbl_rprc_parse.h"
#include "sbl_err_trap.h"
#include "sbl_sci_client.h"
#include "sbl_soc_cfg.h"

#if SBL_USE_DMA
#include "sbl_dma.h"
#endif

/* TI-RTOS Header files */
#include <ti/drv/spi/SPI.h>
#if SBL_USE_DMA
#include <ti/drv/udma/udma.h>
#endif

#include <ti/drv/spi/src/SPI_osal.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/spi/soc/SPI_soc.h>
#include <ti/drv/spi/src/v0/OSPI_v0.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/csl/cslr_device.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/arch/r5/csl_arm_r5.h>
#include <ti/csl/arch/r5/interrupt.h>
#include <ti/board/board_cfg.h>
#include <ti/board/src/flash/include/board_flash.h>
#include "sbl_ospi.h"

/* Macro representing the offset where the App Image has to be written/Read from
   the OSPI Flash.
*/
#define OSPI_OFFSET_SI              (0x100000U)
#define OSPI_OFFSET_SYSFW           (0x80000U)
#define OSPI_MPU_REGION_NUM         (0x6)
#define OSPI_MPU_ENABLE_REGION      (0x1)

/* Macro to specify the counter number */
#define CNTR_NUMBER 0x1F

/* Initialize the OSPI driver and the controller. */
static void SBL_OSPI_Initialize(void);

void SBL_DCacheClean(void *addr, uint32_t size);

void SBL_SysFwLoad(void *dst, void *src, uint32_t size);

static void *boardHandle = NULL;

static OSPI_v0_HwAttrs ospi_cfg;

/* Global variable to check whether BUILD_XIP is defined or not */
bool isXIPEnable = false; 
/* Global variable to check whether OSPI needs to run on 133 MHZ or 166 MHz while booting an application in XIP mode */
uint32_t ospiFrequency;
/* Global variable to check whether OSPI_NAND_BOOT is defined or not */
bool gIsNandBootEnable = false;
/* Global variable to check whether combined ROM boot image format is used or not */
extern uint8_t combinedBootmode;

#if SBL_USE_DMA

/*
 * Ring parameters
 */
/** \brief Number of ring entries - we can prime this much memcpy operations */
#define UDMA_TEST_APP_RING_ENTRIES      (1U)
/** \brief Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
#define UDMA_TEST_APP_RING_ENTRY_SIZE   (sizeof(uint64_t))
/** \brief Total ring memory */
#define UDMA_TEST_APP_RING_MEM_SIZE     (UDMA_TEST_APP_RING_ENTRIES * \
                                         UDMA_TEST_APP_RING_ENTRY_SIZE)
/**
 *  \brief UDMA TR packet descriptor memory.
 *  This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
 *  one Type_15 TR (CSL_UdmapTR15) + one TR response of 4 bytes.
 *  Since CSL_UdmapCppi5TRPD is less than CSL_UdmapTR15, size is just two times
 *  CSL_UdmapTR15 for alignment.
 */
#define UDMA_TEST_APP_TRPD_SIZE         ((sizeof(CSL_UdmapTR15) * 2U) + 4U)

/*
 * UDMA driver objects
 */
struct Udma_DrvObj      gUdmaDrvObj;
struct Udma_ChObj       gUdmaChObj;
struct Udma_EventObj    gUdmaCqEventObj;

static Udma_DrvHandle          gDrvHandle = NULL;
/*
 * UDMA Memories
 */
uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
uint8_t gUdmaTprdMem[UDMA_TEST_APP_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
OSPI_dmaInfo gUdmaInfo;

static int32_t Ospi_udma_deinit(void);
static int32_t Ospi_udma_init(OSPI_v0_HwAttrs *cfg);

static int32_t Ospi_udma_init(OSPI_v0_HwAttrs *cfg)
{
    int32_t         retVal = UDMA_SOK;
    Udma_InitPrms   initPrms;
    uint32_t        instId;

    if (gDrvHandle == (Udma_DrvHandle)uint32_to_void_ptr(0U))
    {
        /* UDMA driver init */
        instId = UDMA_INST_ID_MCU_0;

        UdmaInitPrms_init(instId, &initPrms);
        retVal = Udma_init(&gUdmaDrvObj, &initPrms);
        if(UDMA_SOK == retVal)
        {
            gDrvHandle = &gUdmaDrvObj;
        }
    }

    if(gDrvHandle)
    {
        gUdmaInfo.drvHandle      = (void *)gDrvHandle;
        gUdmaInfo.chHandle       = (void *)&gUdmaChObj;
        gUdmaInfo.ringMem        = (void *)&gTxRingMem[0];
        gUdmaInfo.cqRingMem      = (void *)&gTxCompRingMem[0];
        gUdmaInfo.tdCqRingMem    = (void *)&gTxTdCompRingMem[0];
        gUdmaInfo.tprdMem        = (void *)&gUdmaTprdMem[0];
        gUdmaInfo.eventHandle    = (void *)&gUdmaCqEventObj;
        cfg->dmaInfo             = &gUdmaInfo;
    }

    return (retVal);
}

static int32_t Ospi_udma_deinit(void)
{
    int32_t         retVal = UDMA_SOK;

    if (gDrvHandle)
    {
        retVal = Udma_deinit(gDrvHandle);
        if(UDMA_SOK == retVal)
        {
            gDrvHandle = NULL;
        }
    }

    return (retVal);
}
#endif

int32_t SBL_ReadSysfwImage(void **pBuffer, uint32_t num_bytes)
{
#if !defined(SBL_BYPASS_OSPI_DRIVER) && !defined(SBL_BYPASS_OSPI_DRIVER_FOR_SYSFW_DOWNLOAD)
    Board_flashHandle h;

    /* Init SPI driver */
    OSPI_init();

    /* Get default OSPI cfg */
    OSPI_socGetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

    ospi_cfg.funcClk = OSPI_MODULE_CLK_200M;

    /* false: unstable, cpu read @ 120Mbytes per sec          */
    /*        can work with direct ROM load once it is stable */
    /* true:  stable, CPU read @60Mbytes per sec, will not    */
    /*        work with ROM, as ROM needs byte accesses       */
    ospi_cfg.dtrEnable = true;

    /* OSPI clock is set to 200MHz by RBL on J7200, J721S2 & J784S4 platforms.
     * PHY mode cannot be used until sysfw is loaded and OSPI clock is
     * configured to 133MHz.
     */
#if defined(SIM_BUILD) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
    ospi_cfg.phyEnable = false;
#endif

if (isXIPEnable == true)
{
    ospi_cfg.phyEnable = false;
    /* OSPI baud rate = (master reference clock) / (baud rate devisor)
     * Default baud rate devisor is 32
     * Using a smaller devisor to get higher speeds */
    ospi_cfg.baudRateDiv = 8;
}
else
{
    #if defined(SOC_J721E)
        ospi_cfg.phyEnable = false;
        /* OSPI baud rate = (master reference clock) / (baud rate devisor)
        * Default baud rate devisor is 32
        * Using a smaller devisor to get higher speeds */
        ospi_cfg.baudRateDiv = 8;
    #endif
}

    /* Set the default SPI init configurations */
    if (gIsNandBootEnable == 1)
    {
        ospi_cfg.cacheEnable = 1;
    }
    OSPI_socSetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
    if (gIsNandBootEnable == true)
    {
        h = Board_flashOpen(BOARD_FLASH_ID_W35N01JWTBAG,
                            BOARD_OSPI_NOR_INSTANCE, NULL);
    }
    else
    {
        h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                            BOARD_OSPI_NOR_INSTANCE, NULL);
    }
#else
    h = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
                        BOARD_OSPI_NOR_INSTANCE, NULL);
#endif

    if (h)
    {

        /* Disable PHY pipeline mode */
        CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(ospi_cfg.baseAddr), FALSE);

#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
        /* Until OSPI PHY + DMA is enabled at this early stage, the
         * ROM can more efficiently load the SYSFW directly from xSPI flash */
        if(pBuffer)
        {
            if (gIsNandBootEnable == true)
            {
                if (Board_flashRead(h, OSPI_OFFSET_SYSFW, (uint8_t *) *pBuffer, SBL_SYSFW_MAX_SIZE, NULL))
                {
                    SBL_log(SBL_LOG_ERR, "Board_flashRead failed in SBL_ReadSysfwImage \n");
                    SblErrLoop(__FILE__, __LINE__);
                }
            }
            else
            {
                /* Set up ROM to load system firmware */
                *pBuffer = (void *)(ospi_cfg.dataAddr + OSPI_OFFSET_SYSFW);
            }   /* (gIsNandBootEnable == true) && defined(SOC_J721S2) */
        }
#else
        /* Optimized CPU copy loop - can be removed once ROM load is working */
        SBL_SysFwLoad((void *)(*pBuffer), (void *)(ospi_cfg.dataAddr + OSPI_OFFSET_SYSFW), num_bytes);
#endif

        /* Update handle for later use*/
        boardHandle = (void *)h;
    }
    else
    {
        SBL_log(SBL_LOG_ERR, "Board_flashOpen failed in SBL_ReadSysfwImage \n");
        SblErrLoop(__FILE__, __LINE__);
    }

    return CSL_PASS;
#else

     /* Get default OSPI cfg */
    OSPI_socGetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

   if(pBuffer)
   {
      /* Set up ROM to load system firmware */
      *pBuffer = (void *)(ospi_cfg.dataAddr + OSPI_OFFSET_SYSFW);
   }

   return CSL_PASS;
#endif

}

#if defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
void OSPI_configClk(uint32_t freq)
{
    OSPI_v0_HwAttrs ospi_cfg;
	int32_t retVal;
    uint64_t ospi_rclk_freq;
    uint32_t parClk;
    uint32_t clkID[] = {
                           TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK,
                           TISCI_DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK
    };
    uint32_t devID[] = {
                           TISCI_DEV_MCU_FSS0_OSPI_0,
	                       TISCI_DEV_MCU_FSS0_OSPI_1
    };

    /* Get the default SPI init configurations */
    OSPI_socGetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

    retVal = Sciclient_pmModuleClkRequest(devID[BOARD_OSPI_NOR_INSTANCE],
                                          clkID[BOARD_OSPI_NOR_INSTANCE],
                                          TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ,
                                          TISCI_MSG_FLAG_AOP,
                                          SCICLIENT_SERVICE_WAIT_FOREVER);
    if (retVal != CSL_PASS)
    {
        SBL_log(SBL_LOG_MAX, "Sciclient_pmModuleClkRequest failed \n");
    }

    /* Max clocks */
    if (freq == OSPI_MODULE_CLK_166M)
    {
        parClk = TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK;

        retVal = Sciclient_pmSetModuleClkParent(devID[BOARD_OSPI_NOR_INSTANCE],
                                                clkID[BOARD_OSPI_NOR_INSTANCE],
                                                parClk,
                                                SCICLIENT_SERVICE_WAIT_FOREVER);
    }
    else
    {
        parClk = TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK;
        retVal = Sciclient_pmSetModuleClkParent(devID[BOARD_OSPI_NOR_INSTANCE],
                                                clkID[BOARD_OSPI_NOR_INSTANCE],
                                                parClk,
                                                SCICLIENT_SERVICE_WAIT_FOREVER);
    }

    if (retVal != CSL_PASS)
    {
        SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkParent failed \n");
    }

	ospi_cfg.funcClk = freq;
    OSPI_socSetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

    ospi_rclk_freq = (uint64_t)freq;
    retVal = Sciclient_pmSetModuleClkFreq(devID[BOARD_OSPI_NOR_INSTANCE],
                                          clkID[BOARD_OSPI_NOR_INSTANCE],
                                          ospi_rclk_freq,
                                          TISCI_MSG_FLAG_AOP,
                                          SCICLIENT_SERVICE_WAIT_FOREVER);

    if (retVal != CSL_PASS)
    {
        SBL_log(SBL_LOG_MAX, "Sciclient_pmSetModuleClkFreq failed \n");
    }

	ospi_rclk_freq = 0;
    retVal = Sciclient_pmGetModuleClkFreq(devID[BOARD_OSPI_NOR_INSTANCE],
                                          clkID[BOARD_OSPI_NOR_INSTANCE],
                                          &ospi_rclk_freq,
                                          SCICLIENT_SERVICE_WAIT_FOREVER);
    if (retVal != CSL_PASS)
    {
        SBL_log(SBL_LOG_MAX, "Sciclient_pmGetModuleClkFreq failed \n");
    }

    SBL_log(SBL_LOG_MAX, "OSPI RCLK running at %d MHz. \n", (uint32_t)ospi_rclk_freq);

}
#endif

int32_t SBL_ospiInit(void *handle)
{
#if (!defined(SBL_BYPASS_OSPI_DRIVER) \
     /* In simulation, we must ALWAYS bypass the OSPI driver regardless of what */ \
     /* .. bypass option is requested. REMOVE WHEN SIMULATION IS IRRELEVANT. */ \
     && !(defined(SBL_BYPASS_OSPI_DRIVER_FOR_SYSFW_DOWNLOAD) && defined(SIM_BUILD)))

    Board_flashHandle h = *(Board_flashHandle *) handle;
    static uint32_t enableTuning = TRUE;

    if (h)
    {
        Board_flashClose(h);

    }

    /* Get default OSPI cfg */
    OSPI_socGetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

#if !defined(SBL_SKIP_BRD_CFG_PM) && !defined(SBL_SKIP_SYSFW_INIT)
    {
        /* System Firmware reconfigures the OSPI clock to
         * unsupported values. This is a workaround until
         * that issue is fixed
         */
        uint64_t ospiFunClk;
        if(isXIPEnable == true)
        {
            if(ospiFrequency == 166)
            {
                ospiFunClk = (uint64_t)(OSPI_MODULE_CLK_166M);
                ospi_cfg.devDelays[3] = OSPI_DEV_DELAY_CSDA_3;
            }
            else
            {
                ospiFunClk = (uint64_t)(OSPI_MODULE_CLK_133M);
                ospi_cfg.devDelays[3] = OSPI_DEV_DELAY_CSDA_2;
            }
        }
        else
        {
            #if defined(SOC_J721E) || defined(SOC_J721S2) || defined(SOC_J784S4)
                    ospiFunClk = (uint64_t)(OSPI_MODULE_CLK_166M);
                    ospi_cfg.devDelays[3] = OSPI_DEV_DELAY_CSDA_3;
            #else
                    ospiFunClk = (uint64_t)(OSPI_MODULE_CLK_133M);
                    ospi_cfg.devDelays[3] = OSPI_DEV_DELAY_CSDA_2;
            #endif
        }
        ospi_cfg.funcClk = ospiFunClk;
        ospi_cfg.baudRateDiv = 0;

#if defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
        OSPI_configClk(ospiFunClk);
#else
        struct ospiClkParams
        {
            uint32_t moduleId;
            uint32_t clockId;
        };
        struct ospiClkParams ospiClkInfo[] = {
                                                {SBL_DEV_ID_OSPI0, SBL_CLK_ID_OSPI0},
#ifdef SBL_DEV_ID_OSPI1
                                                {SBL_DEV_ID_OSPI1, SBL_CLK_ID_OSPI1},
#endif
                                            };
        Sciclient_pmSetModuleClkFreq(ospiClkInfo[BOARD_OSPI_NOR_INSTANCE].moduleId, ospiClkInfo[BOARD_OSPI_NOR_INSTANCE].clockId, ospiFunClk, TISCI_MSG_FLAG_AOP, SCICLIENT_SERVICE_WAIT_FOREVER);
        ospi_cfg.funcClk = (uint32_t)ospiFunClk;
        SBL_log(SBL_LOG_MAX, "ospiFunClk = %d Hz \n", ospi_cfg.funcClk);
#endif
    }
#endif

    ospi_cfg.dtrEnable = true;

#if SBL_USE_DMA
    ospi_cfg.dmaEnable = true;
    Ospi_udma_init(&ospi_cfg);

    #if defined(SOC_J721E)
    SBL_udmaInit(gDrvHandle);
    #endif
#endif

#if SBL_USE_DMA
    /* J721E: PHY mode was already previously enabled, so we keep it enabled */
    /* J7200/J721S2/J784S4: Enable the PHY mode which was disabled in SBL_ReadSysfwImage */
    ospi_cfg.phyEnable = true;
#else
#if defined(SOC_J721E)
    ospi_cfg.phyEnable = true;
    ospi_cfg.cacheEnable = true;
#else
    ospi_cfg.phyEnable = false;
#endif
if(isXIPEnable == true)
{
    ospi_cfg.phyEnable = true;
    ospi_cfg.cacheEnable = true;
}
#endif
    /* Set the default SPI init configurations */
    if (gIsNandBootEnable == true)
    {
        ospi_cfg.cacheEnable = 1;
    }
    OSPI_socSetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

    /* Currently there is a dependence for Board_flashClose() to be called before SBL_ospiInit() to reset
     * OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD. In the combined boot case, where SBL_ReadSysfwImage
     * is not called, setting this bit before opening the flash is necessary for clock frequencies of 166 MHz  */
    if(combinedBootmode == TRUE)
    {
        const CSL_ospi_flash_cfgRegs *pRegs = (const CSL_ospi_flash_cfgRegs *)(ospi_cfg.baseAddr);
        CSL_REG32_FINS(&pRegs->RD_DATA_CAPTURE_REG, OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD, 0);

    }

#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
    if (gIsNandBootEnable == true)
    {
        h = Board_flashOpen(BOARD_FLASH_ID_W35N01JWTBAG,
                            BOARD_OSPI_NOR_INSTANCE, (void *)(enableTuning));
    }
    else
    {
        h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                            BOARD_OSPI_NOR_INSTANCE, (void *)(enableTuning));
    }
#else
    h = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
                            BOARD_OSPI_NOR_INSTANCE, (void *)(enableTuning));
#endif
    if (h)
    {
        *(Board_flashHandle *) handle = h;
        /* Update the static handle as well, for later use */
        boardHandle = (void *)h;
#if !(SBL_USE_DMA) && !defined(SOC_J721E)
        if(isXIPEnable == false)
        {
            /* Disable PHY pipeline mode if not using DMA */
            CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(ospi_cfg.baseAddr), FALSE);
        }
#endif
    }
    else
    {
        SBL_log(SBL_LOG_ERR, "Board_flashOpen failed in SBL_ospiInit \n");
        SblErrLoop(__FILE__, __LINE__);
    }

    return 0;
#else
    return 0;
#endif
}

int32_t SBL_ospiFlashRead(const void *handle, uint8_t *dst, uint32_t length,
    uint32_t offset)
{
    uint32_t start_time = CSL_armR5PmuReadCntr(CNTR_NUMBER);
    uint32_t end_time = 0;

#if (!defined(SBL_BYPASS_OSPI_DRIVER) \
     /* In simulation, we must ALWAYS bypass the OSPI driver regardless of what */ \
     /* .. bypass option is requested. REMOVE WHEN SIMULATION IS IRRELEVANT. */ \
     && !(defined(SBL_BYPASS_OSPI_DRIVER_FOR_SYSFW_DOWNLOAD) && defined(SIM_BUILD)))

#if SBL_USE_DMA
    Board_flashHandle h = *(const Board_flashHandle *) handle;
    uint32_t ioMode = OSPI_FLASH_OCTAL_READ;

    if (length > 4 * 1024)
    {
        /* split transfer if not reading from 16 byte aligned flash offset */
        uint32_t dma_offset  = (offset + 0xF) & (~0xF);
        uint32_t non_aligned_bytes = dma_offset - offset;
        uint8_t *dma_dst = (dst + non_aligned_bytes);
        uint32_t dma_len = length - non_aligned_bytes;

        SBL_DCacheClean((void *)dst, length);

        if ((non_aligned_bytes) && (Board_flashRead(h, offset, dst, non_aligned_bytes, (void *)(&ioMode))))
        {
            SBL_log(SBL_LOG_ERR, "Board_flashRead failed!\n");
            SblErrLoop(__FILE__, __LINE__);
        }

        if (Board_flashRead(h, dma_offset, dma_dst, dma_len, (void *)(&ioMode)))
        {
            SBL_log(SBL_LOG_ERR, "Board_flashRead failed!\n");
            SblErrLoop(__FILE__, __LINE__);
        }
    }
    else
    {
        SBL_DCacheClean((void *)dst, length);
        Board_flashRead(h, offset, dst, length, (void *)(&ioMode));
    }

#else

    if((isXIPEnable == true) || (gIsNandBootEnable == true))
    {
        Board_flashHandle h = *(const Board_flashHandle *) handle;
        uint32_t ioMode = OSPI_FLASH_OCTAL_READ;
        SBL_DCacheClean((void *)dst, length);
        Board_flashRead(h, offset, dst, length, (void *)(&ioMode));
    }
    else
    {
        /* Due to change in phy tuning algo, it is taking around to 40ms for tuning.
           As a workaround using memcpy instead of Board_flashRead(). This should be 
           reverted after fixing PDK-13114 */
        // #if defined(SOC_J721E)
        //     Board_flashHandle h = *(const Board_flashHandle *) handle;
        //     uint32_t ioMode = OSPI_FLASH_OCTAL_READ;
        //     SBL_DCacheClean((void *)dst, length);
        //     Board_flashRead(h, offset, dst, length, (void *)(&ioMode));
        // #else 
        memcpy((void *)dst, (void *)(ospi_cfg.dataAddr + offset), length);
        // #endif
    }

#endif /* #if SBL_USE_DMA */

#else
    memcpy((void *)dst, (void *)(ospi_cfg.dataAddr + offset), length);
#endif /* #if !defined(SBL_BYPASS_OSPI_DRIVER) */

    end_time = CSL_armR5PmuReadCntr(CNTR_NUMBER);

    SBL_log(SBL_LOG_MAX, "Ospi Read speed for 0x%x bytes from offset 0x%x = %d Mbytes per sec\n", length, offset, ((400000000 / (end_time-start_time)) * length)/0x100000);

    return 0;
}

int32_t SBL_ospiClose(const void *handle)
{
#if (!defined(SBL_BYPASS_OSPI_DRIVER) \
     /* In simulation, we must ALWAYS bypass the OSPI driver regardless of what */ \
     /* .. bypass option is requested. REMOVE WHEN SIMULATION IS IRRELEVANT. */ \
     && !(defined(SBL_BYPASS_OSPI_DRIVER_FOR_SYSFW_DOWNLOAD) && defined(SIM_BUILD)))

    Board_flashHandle h = *(const Board_flashHandle *) handle;

    SBL_log(SBL_LOG_MAX, "SBL_ospiClose called\n");
    Board_flashClose(h);
#if SBL_USE_DMA
    #if defined(SOC_J721E)
    SBL_udmaDeInit();
    #endif
    Ospi_udma_deinit();
#endif
#else
#endif
    return 0;
}

#if defined(SBL_HLOS_OWNS_FLASH) && !defined(SBL_USE_MCU_DOMAIN_ONLY)
/* Only put OSPI flash back into SPI mode if we're going to directly boot ATF/U-boot/Linux from SBL */
int32_t SBL_ospiLeaveConfigSPI()
{
    int32_t retVal = E_PASS;
    Board_flashHandle h;
    Board_FlashInfo *flashInfo;

    /* Get default OSPI cfg */
    OSPI_socGetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

    ospi_cfg.funcClk = OSPI_MODULE_CLK_133M;
    /* Configure the flash for SPI mode */
    ospi_cfg.xferLines = OSPI_XFER_LINES_SINGLE;
    /* Put controller in DAC mode so flash ID can be read directly */
    ospi_cfg.dacEnable = true;
    /* Disable PHY in legacy SPI mode (1-1-1) */
    ospi_cfg.phyEnable = false;
    ospi_cfg.dtrEnable = false;
    ospi_cfg.xipEnable = false;

    /* Set the default SPI init configurations */
    OSPI_socSetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);

#if defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4)
    if (gIsNandBootEnable == true)
    {
        h = Board_flashOpen(BOARD_FLASH_ID_W35N01JWTBAG,
                            BOARD_OSPI_NOR_INSTANCE, NULL);
    }
    else
    {
        h = Board_flashOpen(BOARD_FLASH_ID_S28HS512T,
                            BOARD_OSPI_NOR_INSTANCE, NULL);
    }
#else
    h = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
                        BOARD_OSPI_NOR_INSTANCE, NULL);
#endif

    if (h)
    {
        SBL_log(SBL_LOG_MAX, "OSPI flash left configured in Legacy SPI mode.\n");
        flashInfo = (Board_FlashInfo *)h;
        SBL_log(SBL_LOG_MAX, "\n OSPI NOR device ID: 0x%x, manufacturer ID: 0x%x \n",
                flashInfo->device_id, flashInfo->manufacturer_id);
        Board_flashClose(h);
    }
    else
    {
        SBL_log(SBL_LOG_ERR, "Board_flashOpen failed in SPI mode!!\n");
        retVal = E_FAIL;
    }


    return(retVal);
}
#endif

int32_t SBL_OSPIBootImage(sblEntryPoint_t *pEntry)
{
    int32_t retVal;
    uint32_t offset = OSPI_OFFSET_SI;

    SBL_ADD_PROFILE_POINT;
    /* Initialization of the driver. */
    SBL_OSPI_Initialize();

#if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4))
    retVal =  SBL_MulticoreImageParse((void *) &offset, OSPI_OFFSET_SI, pEntry, SBL_SKIP_BOOT_AFTER_COPY);
#else
    SBL_ADD_PROFILE_POINT;
    retVal =  SBL_MulticoreImageParse((void *) &offset, OSPI_OFFSET_SI, pEntry, SBL_BOOT_AFTER_COPY);
#endif

    SBL_ospiClose(&boardHandle);

if(isXIPEnable == true)
{
    #if (defined(SOC_J7200) || defined(SOC_J721S2) || defined(SOC_J784S4))
        /* These fields are reset by Nor_xspiClose but are required for XIP */

        const CSL_ospi_flash_cfgRegs *pRegs = (const CSL_ospi_flash_cfgRegs *)(ospi_cfg.baseAddr);

        CSL_REG32_FINS(&pRegs->RD_DATA_CAPTURE_REG,
                        OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_SAMPLE_EDGE_SEL_FLD,
                        1);

        CSL_REG32_FINS(&pRegs->RD_DATA_CAPTURE_REG,
                        OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG_DQS_ENABLE_FLD,
                        1);
    #endif
}

#if defined(SBL_HLOS_OWNS_FLASH) && !defined(SBL_USE_MCU_DOMAIN_ONLY)
/* Only put OSPI flash back into SPI mode if we're going to directly boot ATF/U-boot/Linux from SBL */
    SBL_ospiLeaveConfigSPI();
#endif

    return retVal;
}

static void SBL_OSPI_Initialize(void)
{
    SBL_ospiInit(&boardHandle);

    /* Initialize the function pointers to parse through the RPRC format. */
    fp_readData = &SBL_OSPI_ReadSectors;
    fp_seek     = &SBL_OSPI_seek;
}

void SBL_SPI_init()
{
    OSPI_init();
}

int32_t SBL_OSPI_ReadSectors(void *dstAddr,
                             void *srcOffsetAddr,
                             uint32_t length)
{
    int32_t ret;
    ret = SBL_ospiFlashRead(&boardHandle, (uint8_t *) dstAddr, length,
        *((uint32_t *) srcOffsetAddr));
    *((uint32_t *) srcOffsetAddr) += length;
    return ret;
}

void SBL_OSPI_seek(void *srcAddr, uint32_t location)
{
    *((uint32_t *) srcAddr) = location;
}

void SBL_enableXIPMode(uint32_t freq)
{
    isXIPEnable = true;
    ospiFrequency = freq;
}

void SBL_enableNandBoot()
{
    gIsNandBootEnable = true;
}

m35xu512.h

/*
 * Copyright (c) 2018 - 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *
 * \file  m35xu512.h
 *
 * \brief This file contains M35XU512 NOR device definitions
 *
 *****************************************************************************/
#ifndef M35XU512_H_
#define M35XU512_H_

#include <ti/drv/spi/SPI.h>

/**************************************************************************
 **                       Macro Definitions
 **************************************************************************/

/** Macro to enable 4 byte addressing */
/* #define EXT_ADDRESS_ENABLE        (0U) */

/** FLASH device specific items (note: sizes are in bytes) */
#define NOR_BLOCK_SIZE               (128U * 1024U)
#define NOR_SECTOR_SIZE              (4U * 1024U)
#define NOR_SIZE                     (64U * 1024U * 1024U)
#define NOR_NUM_BLOCKS               (NOR_SIZE / NOR_BLOCK_SIZE)
#define NOR_NUM_SECTORS              (NOR_SIZE / NOR_SECTOR_SIZE)
#define NOR_PAGE_SIZE                (256U)
#define NOR_NUM_PAGES_PER_SECTOR     (NOR_SECTOR_SIZE / NOR_PAGE_SIZE)
#define NOR_NUM_PAGES_PER_BLOCK      (NOR_BLOCK_SIZE / NOR_PAGE_SIZE)

/** Flash device commands */
#define NOR_BE_SECTOR_NUM            (-1U)
#define NOR_CMD_BULK_ERASE           (0x60U)
#define NOR_CMD_WRR                  (0x01U)
#define NOR_CMD_WREN                 (0x06U)
#define NOR_CMD_RDSR                 (0x05U)
#define NOR_CMD_RDCR_VOL             (0x85U)
#define NOR_CMD_RDCR_NVOL            (0xB5U)
#define NOR_CMD_RDID                 (0x9FU)
#define NOR_CMD_RSTEN                (0x66U)
#define NOR_CMD_RST_MEM              (0x99U)

/** Different commands for 4 byte addressing and 3 byte addressing */
#ifdef EXT_ADDRESS_ENABLE
#define NOR_CMD_BLOCK_ERASE          (0xDCU)
#define NOR_CMD_SECTOR_ERASE         (0x21U)
#define NOR_CMD_READ                 (0x13U)
#define NOR_CMD_FAST_READ            (0x0CU)
#define NOR_CMD_OCTAL_O_FAST_RD      (0x7CU)
#define NOR_CMD_OCTAL_IO_FAST_RD     (0xCCU)
#define NOR_CMD_OCTAL_READ           (NOR_CMD_OCTAL_O_FAST_RD)
#define NOR_CMD_PAGE_PROG            (0x12U)
#define NOR_CMD_OCTAL_FAST_PROG      (0x84U)
#define NOR_CMD_EXT_OCTAL_FAST_PROG  (0x8EU)
#define NOR_CMD_OCTAL_PROG           (NOR_CMD_OCTAL_FAST_PROG)
#else
#define NOR_CMD_BLOCK_ERASE          (0xD8U)
#define NOR_CMD_SECTOR_ERASE         (0x20U)
#define NOR_CMD_READ                 (0x03U)
#define NOR_CMD_FAST_READ            (0x0BU)
#define NOR_CMD_OCTAL_O_FAST_RD      (0x8BU)
#define NOR_CMD_OCTAL_IO_FAST_RD     (0xCBU)
#define NOR_CMD_OCTAL_DDR_O_FAST_RD  (0x9DU)
#define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xFDU)
#define NOR_CMD_OCTAL_READ           (NOR_CMD_OCTAL_O_FAST_RD)
#define NOR_CMD_PAGE_PROG            (0x02U)
#define NOR_CMD_OCTAL_FAST_PROG      (0x82U)
#define NOR_CMD_EXT_OCTAL_FAST_PROG  (0xC2U)
#define NOR_CMD_OCTAL_PROG           (NOR_CMD_OCTAL_FAST_PROG)
#define NOR_CMD_WRITE_VCR            (0x81U)
#define NOR_CMD_READ_VCR             (0x85U)
#endif

/* \brief Read ID command definitions */
#define NOR_RDID_NUM_BYTES           (0x3U)
#define NOR_MANF_ID                  (0x2CU)    /* Manufacturer ID */
//#define NOR_DEVICE_ID                (0x5B1A)   /* Device ID */
#define NOR_DEVICE_ID                (0x5B1C)   /* Device ID */

/** Status Register, Write-in-Progress bit */
#define NOR_SR_WIP                   (1U << 0U)

/** Dummy cycles for Read operation */
/** Dummy cycles for Read operation */
#define NOR_SINGLE_READ_DUMMY_CYCLE  (0U)
#define NOR_OCTAL_READ_DUMMY_CYCLE   (30U)


/** In Micro seconds */
#define NOR_PAGE_PROG_TIMEOUT        (400U)
#define NOR_SECTOR_ERASE_TIMEOUT     (600U * 1000U)
#define NOR_WRR_WRITE_TIMEOUT        (600U * 1000U)
#define NOR_BULK_ERASE_TIMEOUT       (110U * 1000U * 1000U)

#endif /* M35XU512_H_ */

/* Nothing past this point */

ddrReginit.h

/* Copyright (c) 2019, Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */

/*
 * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0
 * This file was generated on 10/16/2023
 * 
 * THIS IS FOR ZF IPM6
*/

#define DDRSS_PLL_FHS_CNT 10
#define DDRSS_PLL_FREQUENCY_0 27500000
#define DDRSS_PLL_FREQUENCY_1 800000000
#define DDRSS_PLL_FREQUENCY_2 800000000

#define DDRSS_CTL_REG_INIT_COUNT (459U)
#define DDRSS_PHY_INDEP_REG_INIT_COUNT (300U)
#define DDRSS_PHY_REG_INIT_COUNT (1423U)

uint32_t DDRSS_ctlReg[] = {
    0x00000B00U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00002AF8U,
    0x0001ADAFU,
    0x00000005U,
    0x0000006EU,
    0x0004E200U,
    0x0030D400U,
    0x00000005U,
    0x00000C80U,
    0x0004E200U,
    0x0030D400U,
    0x00000005U,
    0x00000C80U,
    0x01010000U,
    0x02011001U,
    0x02010000U,
    0x00020100U,
    0x0000000BU,
    0x0000001CU,
    0x00000000U,
    0x00000000U,
    0x03020200U,
    0x00004040U,
    0x00100000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x040C0000U,
    0x12481248U,
    0x00050804U,
    0x09040008U,
    0x10000204U,
    0x15480068U,
    0x10003120U,
    0x15480068U,
    0x20003120U,
    0x000A0A09U,
    0x040003C5U,
    0x17100D04U,
    0x0C006DB0U,
    0x17100D0CU,
    0x0C006DB0U,
    0x0203040CU,
    0x21040500U,
    0x08222122U,
    0x14000E0AU,
    0x03010A0AU,
    0x01010003U,
    0x04424208U,
    0x04252504U,
    0x00002525U,
    0x00010100U,
    0x03010000U,
    0x00001008U,
    0x00000063U,
    0x000001C0U,
    0x00000C28U,
    0x000001C0U,
    0x00000C28U,
    0x00000005U,
    0x00040000U,
    0x00700012U,
    0x00700304U,
    0x00400304U,
    0x00120103U,
    0x000C0005U,
    0x2408000CU,
    0x05050124U,
    0x0301030AU,
    0x03170C08U,
    0x0C080301U,
    0x00010317U,
    0x00100010U,
    0x01CC01CCU,
    0x01CC01CCU,
    0x03050505U,
    0x03010303U,
    0x18080C08U,
    0x03030C03U,
    0x18080C08U,
    0x03030C03U,
    0x03010000U,
    0x00010000U,
    0x00000000U,
    0x00000000U,
    0x01000000U,
    0x80104002U,
    0x00000000U,
    0x00040005U,
    0x00000000U,
    0x00050000U,
    0x00000004U,
    0x00000000U,
    0x00040005U,
    0x00000000U,
    0x000018C0U,
    0x000018C0U,
    0x000018C0U,
    0x000018C0U,
    0x000018C0U,
    0x00000000U,
    0x000002B5U,
    0x00030A00U,
    0x00030A00U,
    0x00030A00U,
    0x00030A00U,
    0x00030A00U,
    0x00000000U,
    0x00005518U,
    0x00030A00U,
    0x00030A00U,
    0x00030A00U,
    0x00030A00U,
    0x00030A00U,
    0x00000000U,
    0x00005518U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x08030500U,
    0x00030803U,
    0x0A090000U,
    0x0A090701U,
    0x0900000EU,
    0x0907010AU,
    0x00000E0AU,
    0x07010A09U,
    0x000E0A09U,
    0x07000401U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x08080000U,
    0x01000000U,
    0x800000C0U,
    0x800000C0U,
    0x800000C0U,
    0x00000000U,
    0x00001500U,
    0x00000000U,
    0x00000001U,
    0x00000002U,
    0x0000100EU,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x000B0000U,
    0x000E0006U,
    0x000E0404U,
    0x00A00140U,
    0x0C0C0190U,
    0x01400190U,
    0x019000A0U,
    0x01900C0CU,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x3FF40084U,
    0x33003FF4U,
    0x00003333U,
    0x56000000U,
    0x27270056U,
    0x0F0F0000U,
    0x16000000U,
    0x00841616U,
    0x3FF43FF4U,
    0x33333300U,
    0x00000000U,
    0x00565600U,
    0x00002727U,
    0x00000F0FU,
    0x16161600U,
    0x00000020U,
    0x00000000U,
    0x00000001U,
    0x00000000U,
    0x01000000U,
    0x00000001U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x02000000U,
    0x01080101U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00001000U,
    0x006403E8U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x15110000U,
    0x00040C18U,
    0xF000C000U,
    0x0000F000U,
    0x00000000U,
    0x00000000U,
    0xC0000000U,
    0xF000F000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0xF000C000U,
    0x0000F000U,
    0x00000000U,
    0x00000000U,
    0x00030000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x01000200U,
    0x00370040U,
    0x00020008U,
    0x00400100U,
    0x00300640U,
    0x01000200U,
    0x06400040U,
    0x00000030U,
    0x00500003U,
    0x01000050U,
    0x03030303U,
    0x01010000U,
    0x00000202U,
    0x00000FFFU,
    0x1FFF1000U,
    0x01FF0000U,
    0x000101FFU,
    0x0FFF0B00U,
    0x01010001U,
    0x01010101U,
    0x01180101U,
    0x00030000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00040101U,
    0x04010100U,
    0x00000000U,
    0x00000000U,
    0x03030300U,
    0x00000001U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x01000000U,
    0x00020201U,
    0x01000101U,
    0x01010001U,
    0x00010101U,
    0x050C0C03U,
    0x0C082020U,
    0x0009030CU,
    0x090D030FU,
    0x090D0306U,
    0x0D090006U,
    0x0100000DU,
    0x06030601U,
    0x00000003U,
    0x00000000U,
    0x00010000U,
    0x00280D00U,
    0x00000001U,
    0x00030001U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x01000000U,
    0x00000001U,
    0x00010100U,
    0x03030000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x000556AAU,
    0x000AAAAAU,
    0x000AA955U,
    0x00055555U,
    0x000B3133U,
    0x0004CD33U,
    0x0004CECCU,
    0x000B32CCU,
    0x00010300U,
    0x03000100U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00010000U,
    0x00000404U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x33331B00U,
    0x000A0000U,
    0x000000C6U,
    0x00000200U,
    0x00000200U,
    0x00000200U,
    0x00000200U,
    0x00000252U,
    0x000007BCU,
    0x00000204U,
    0x00001850U,
    0x00000200U,
    0x00000200U,
    0x00000200U,
    0x00000200U,
    0x000048F0U,
    0x0000F320U,
    0x00000E18U,
    0x00001850U,
    0x00000200U,
    0x00000200U,
    0x00000200U,
    0x00000200U,
    0x000048F0U,
    0x0000F320U,
    0x02020E18U,
    0x03030202U,
    0x00000022U,
    0x00000000U,
    0x00000000U,
    0x00001403U,
    0x000007D0U,
    0x00000000U,
    0x00000000U,
    0x00030000U,
    0x0007001FU,
    0x0016002EU,
    0x0016002EU,
    0x00000000U,
    0x00000000U,
    0x02000000U,
    0x01000404U,
    0x0B1E0B1EU,
    0x00000105U,
    0x00010101U,
    0x00010101U,
    0x00010001U,
    0x00000101U,
    0x02000201U,
    0x02010000U,
    0x00000200U,
    0x28060000U,
    0x00000128U,
    0xFFFFFFFFU,
    0xFFFFFFFFU,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
};

uint32_t DDRSS_phyIndepReg[] = {
    0x00000B00U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000101U,
    0x00640000U,
    0x00000001U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000007U,
    0x00010002U,
    0x0800000FU,
    0x00000103U,
    0x00000005U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00010100U,
    0x00280A00U,
    0x00000000U,
    0x0F000000U,
    0x00003200U,
    0x00000000U,
    0x00000000U,
    0x01010102U,
    0x00000000U,
    0x000000AAU,
    0x00000055U,
    0x000000B5U,
    0x0000004AU,
    0x00000056U,
    0x000000A9U,
    0x000000A9U,
    0x000000B5U,
    0x00000000U,
    0x00000000U,
    0x000F0F00U,
    0x00000019U,
    0x000007D0U,
    0x00000300U,
    0x00000000U,
    0x00000000U,
    0x01000000U,
    0x00010101U,
    0x00000000U,
    0x00030000U,
    0x0F000000U,
    0x00000017U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x0A0A140AU,
    0x10020101U,
    0x00020805U,
    0x01000404U,
    0x00000000U,
    0x00000000U,
    0x00000100U,
    0x0001010FU,
    0x00340000U,
    0x00000000U,
    0x00000000U,
    0x0000FFFFU,
    0x00000000U,
    0x00080100U,
    0x02000200U,
    0x01000100U,
    0x01000000U,
    0x02000200U,
    0x00000200U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000400U,
    0x02010000U,
    0x00080003U,
    0x00080000U,
    0x00000001U,
    0x00000000U,
    0x0000AA00U,
    0x00000000U,
    0x00000000U,
    0x00010000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000008U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000002U,
    0x00000000U,
    0x00000000U,
    0x0000000AU,
    0x00000019U,
    0x00000100U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x01000000U,
    0x00010003U,
    0x02000101U,
    0x01030001U,
    0x00010400U,
    0x06000105U,
    0x01070001U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00010001U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000401U,
    0x00000000U,
    0x00010000U,
    0x00000000U,
    0x20200200U,
    0x00000034U,
    0x00000060U,
    0x00020060U,
    0x02000200U,
    0x48120C04U,
    0x00104812U,
    0x00000063U,
    0x000001C0U,
    0x00000C28U,
    0x000001C0U,
    0x04000C28U,
    0x01010404U,
    0x00001501U,
    0x00150015U,
    0x01000100U,
    0x00000100U,
    0x00000000U,
    0x01010101U,
    0x00000101U,
    0x00000000U,
    0x00000000U,
    0x18040000U,
    0x0E0E0218U,
    0x00040402U,
    0x000D0035U,
    0x001C0044U,
    0x001C0044U,
    0x01010101U,
    0x0003000EU,
    0x00030190U,
    0x01000190U,
    0x000F000FU,
    0x01910100U,
    0x01000191U,
    0x01910191U,
    0x32103200U,
    0x01013210U,
    0x0A070601U,
    0x180F090DU,
    0x180F0911U,
    0x0000C011U,
    0x00C01000U,
    0x00C01000U,
    0x00021000U,
    0x001E000EU,
    0x001E0190U,
    0x00110190U,
    0x32000056U,
    0x00000301U,
    0x005E0034U,
    0x03013212U,
    0x00003400U,
    0x3212005EU,
    0x09000301U,
    0x04010504U,
    0x04000364U,
    0x0A032001U,
    0x21250D0AU,
    0x00002216U,
    0x480062B8U,
    0x17182006U,
    0x21250D10U,
    0x00002216U,
    0x480062B8U,
    0x17182006U,
    0x0000C610U,
    0x000007BCU,
    0x00001850U,
    0x0000F320U,
    0x00001850U,
    0x0000F320U,
    0x01CC0010U,
    0x030301CCU,
    0x002AF803U,
    0x0001ADAFU,
    0x00000005U,
    0x0000006EU,
    0x00000010U,
    0x0004E200U,
    0x0001ADAFU,
    0x00000005U,
    0x00000C80U,
    0x000001CCU,
    0x0004E200U,
    0x0001ADAFU,
    0x00000005U,
    0x00000C80U,
    0x010001CCU,
    0x00370040U,
    0x00010008U,
    0x06400040U,
    0x00010030U,
    0x06400040U,
    0x00000330U,
    0x00500050U,
    0x08040404U,
    0x00000055U,
    0x55083C5AU,
    0x5A000000U,
    0x0055083CU,
    0x3C5A0000U,
    0x00005508U,
    0x0C3C5A00U,
    0x080F0E0DU,
    0x000B0A09U,
    0x00030201U,
    0x01000000U,
    0x04020201U,
    0x00080804U,
    0x00000000U,
    0x00000000U,
    0x00330084U,
    0x00160000U,
    0x56333FF4U,
    0x00160F27U,
    0x56333FF4U,
    0x00160F27U,
    0x00330084U,
    0x00160000U,
    0x56333FF4U,
    0x00160F27U,
    0x56333FF4U,
    0x00160F27U,
    0x00330084U,
    0x00160000U,
    0x56333FF4U,
    0x00160F27U,
    0x56333FF4U,
    0x00160F27U,
    0x00330084U,
    0x00160000U,
    0x56333FF4U,
    0x00160F27U,
    0x56333FF4U,
    0x00160F27U,
    0x00000000U,
};

uint32_t DDRSS_phyReg[] = {
    0x000004F0U,
    0x00000000U,
    0x00030200U,
    0x00000000U,
    0x00000000U,
    0x01030000U,
    0x00010000U,
    0x01030004U,
    0x01000000U,
    0x00000000U,
    0x00000000U,
    0x01000001U,
    0x00000100U,
    0x000800C0U,
    0x060100CCU,
    0x00030066U,
    0x00000000U,
    0x00000301U,
    0x0000AAAAU,
    0x00005555U,
    0x0000B5B5U,
    0x00004A4AU,
    0x00005656U,
    0x0000A9A9U,
    0x0000A9A9U,
    0x0000B5B5U,
    0x00000000U,
    0x00000000U,
    0x2A000000U,
    0x00000808U,
    0x0F000000U,
    0x00000F0FU,
    0x10400000U,
    0x0C002006U,
    0x00000000U,
    0x00000000U,
    0x55555555U,
    0xAAAAAAAAU,
    0x55555555U,
    0xAAAAAAAAU,
    0x00005555U,
    0x01000100U,
    0x00800180U,
    0x00000001U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000104U,
    0x00000120U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000001U,
    0x07FF0000U,
    0x0080081FU,
    0x00081020U,
    0x04010000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000100U,
    0x01CC0C01U,
    0x1003CC0CU,
    0x20000140U,
    0x07FF0200U,
    0x0000DD01U,
    0x10100303U,
    0x10101010U,
    0x10101010U,
    0x00021010U,
    0x00100010U,
    0x00100010U,
    0x00100010U,
    0x00100010U,
    0x00050010U,
    0x51517041U,
    0x31C06000U,
    0x07AB0340U,
    0x00C0C001U,
    0x0B0A0001U,
    0x10001000U,
    0x0C073E42U,
    0x0F0C2D01U,
    0x01000140U,
    0x0C000420U,
    0x00000198U,
    0x0A0000D0U,
    0x00030200U,
    0x02800000U,
    0x80800000U,
    0x000B2010U,
    0x76543210U,
    0x00000008U,
    0x02800280U,
    0x02800280U,
    0x02800280U,
    0x02800280U,
    0x00000280U,
    0x0000A000U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x011900A0U,
    0x01A00004U,
    0x00000000U,
    0x00000000U,
    0x00080200U,
    0x00000000U,
    0x20202000U,
    0x20202020U,
    0xF0F02020U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x000004F0U,
    0x00000000U,
    0x00030200U,
    0x00000000U,
    0x00000000U,
    0x01030000U,
    0x00010000U,
    0x01030004U,
    0x01000000U,
    0x00000000U,
    0x00000000U,
    0x01000001U,
    0x00000100U,
    0x000800C0U,
    0x060100CCU,
    0x00030066U,
    0x00000000U,
    0x00000301U,
    0x0000AAAAU,
    0x00005555U,
    0x0000B5B5U,
    0x00004A4AU,
    0x00005656U,
    0x0000A9A9U,
    0x0000A9A9U,
    0x0000B5B5U,
    0x00000000U,
    0x00000000U,
    0x2A000000U,
    0x00000808U,
    0x0F000000U,
    0x00000F0FU,
    0x10400000U,
    0x0C002006U,
    0x00000000U,
    0x00000000U,
    0x55555555U,
    0xAAAAAAAAU,
    0x55555555U,
    0xAAAAAAAAU,
    0x00005555U,
    0x01000100U,
    0x00800180U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000104U,
    0x00000120U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000001U,
    0x07FF0000U,
    0x0080081FU,
    0x00081020U,
    0x04010000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000100U,
    0x01CC0C01U,
    0x1003CC0CU,
    0x20000140U,
    0x07FF0200U,
    0x0000DD01U,
    0x10100303U,
    0x10101010U,
    0x10101010U,
    0x00021010U,
    0x00100010U,
    0x00100010U,
    0x00100010U,
    0x00100010U,
    0x00050010U,
    0x51517041U,
    0x31C06000U,
    0x07AB0340U,
    0x00C0C001U,
    0x0B0A0001U,
    0x10001000U,
    0x0C073E42U,
    0x0F0C2D01U,
    0x01000140U,
    0x0C000420U,
    0x00000198U,
    0x0A0000D0U,
    0x00030200U,
    0x02800000U,
    0x80800000U,
    0x000B2010U,
    0x76543210U,
    0x00000008U,
    0x02800280U,
    0x02800280U,
    0x02800280U,
    0x02800280U,
    0x00000280U,
    0x0000A000U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x00A000A0U,
    0x011900A0U,
    0x01A00004U,
    0x00000000U,
    0x00000000U,
    0x00080200U,
    0x00000000U,
    0x20202000U,
    0x20202020U,
    0xF0F02020U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
    0x00000000U,
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    0x000100F0U,
    0x780DFFCCU,
    0x00007E31U,
    0x000CBF11U,
    0x01990010U,
    0x000CBF11U,
    0x01990010U,
    0x3F0DFF11U,
    0x019900F0U,
    0x3F0DFF11U,
    0x01FF00F0U,
    0x20040006U,
};


uint16_t DDRSS_ctlRegNum[] = {
    0,
    1,
    2,
    3,
    4,
    5,
    6,
    7,
    8,
    9,
    10,
    11,
    12,
    13,
    14,
    15,
    16,
    17,
    18,
    19,
    20,
    21,
    22,
    23,
    24,
    25,
    26,
    27,
    28,
    29,
    30,
    31,
    32,
    33,
    34,
    35,
    36,
    37,
    38,
    39,
    40,
    41,
    42,
    43,
    44,
    45,
    46,
    47,
    48,
    49,
    50,
    51,
    52,
    53,
    54,
    55,
    56,
    57,
    58,
    59,
    60,
    61,
    62,
    63,
    64,
    65,
    66,
    67,
    68,
    69,
    70,
    71,
    72,
    73,
    74,
    75,
    76,
    77,
    78,
    79,
    80,
    81,
    82,
    83,
    84,
    85,
    86,
    87,
    88,
    89,
    90,
    91,
    92,
    93,
    94,
    95,
    96,
    97,
    98,
    99,
    100,
    101,
    102,
    103,
    104,
    105,
    106,
    107,
    108,
    109,
    110,
    111,
    112,
    113,
    114,
    115,
    116,
    117,
    118,
    119,
    120,
    121,
    122,
    123,
    124,
    125,
    126,
    127,
    128,
    129,
    130,
    131,
    132,
    133,
    134,
    135,
    136,
    137,
    138,
    139,
    140,
    141,
    142,
    143,
    144,
    145,
    146,
    147,
    148,
    149,
    150,
    151,
    152,
    153,
    154,
    155,
    156,
    157,
    158,
    159,
    160,
    161,
    162,
    163,
    164,
    165,
    166,
    167,
    168,
    169,
    170,
    171,
    172,
    173,
    174,
    175,
    176,
    177,
    178,
    179,
    180,
    181,
    182,
    183,
    184,
    185,
    186,
    187,
    188,
    189,
    190,
    191,
    192,
    193,
    194,
    195,
    196,
    197,
    198,
    199,
    200,
    201,
    202,
    203,
    204,
    205,
    206,
    207,
    208,
    209,
    210,
    211,
    212,
    213,
    214,
    215,
    216,
    217,
    218,
    219,
    220,
    221,
    222,
    223,
    224,
    225,
    226,
    227,
    228,
    229,
    230,
    231,
    232,
    233,
    234,
    235,
    236,
    237,
    238,
    239,
    240,
    241,
    242,
    243,
    244,
    245,
    246,
    247,
    248,
    249,
    250,
    251,
    252,
    253,
    254,
    255,
    256,
    257,
    258,
    259,
    260,
    261,
    262,
    263,
    264,
    265,
    266,
    267,
    268,
    269,
    270,
    271,
    272,
    273,
    274,
    275,
    276,
    277,
    278,
    279,
    280,
    281,
    282,
    283,
    284,
    285,
    286,
    287,
    288,
    289,
    290,
    291,
    292,
    293,
    294,
    295,
    296,
    297,
    298,
    299,
    300,
    301,
    302,
    303,
    304,
    305,
    306,
    307,
    308,
    309,
    310,
    311,
    312,
    313,
    314,
    315,
    316,
    317,
    318,
    319,
    320,
    321,
    322,
    323,
    324,
    325,
    326,
    327,
    328,
    329,
    330,
    331,
    332,
    333,
    334,
    335,
    336,
    337,
    338,
    339,
    340,
    341,
    342,
    343,
    344,
    345,
    346,
    347,
    348,
    349,
    350,
    351,
    352,
    353,
    354,
    355,
    356,
    357,
    358,
    359,
    360,
    361,
    362,
    363,
    364,
    365,
    366,
    367,
    368,
    369,
    370,
    371,
    372,
    373,
    374,
    375,
    376,
    377,
    378,
    379,
    380,
    381,
    382,
    383,
    384,
    385,
    386,
    387,
    388,
    389,
    390,
    391,
    392,
    393,
    394,
    395,
    396,
    397,
    398,
    399,
    400,
    401,
    402,
    403,
    404,
    405,
    406,
    407,
    408,
    409,
    410,
    411,
    412,
    413,
    414,
    415,
    416,
    417,
    418,
    419,
    420,
    421,
    422,
    423,
    424,
    425,
    426,
    427,
    428,
    429,
    430,
    431,
    432,
    433,
    434,
    435,
    436,
    437,
    438,
    439,
    440,
    441,
    442,
    443,
    444,
    445,
    446,
    447,
    448,
    449,
    450,
    451,
    452,
    453,
    454,
    455,
    456,
    457,
    458,
};

uint16_t DDRSS_phyIndepRegNum[] = {
    0,
    1,
    2,
    3,
    4,
    5,
    6,
    7,
    8,
    9,
    10,
    11,
    12,
    13,
    14,
    15,
    16,
    17,
    18,
    19,
    20,
    21,
    22,
    23,
    24,
    25,
    26,
    27,
    28,
    29,
    30,
    31,
    32,
    33,
    34,
    35,
    36,
    37,
    38,
    39,
    40,
    41,
    42,
    43,
    44,
    45,
    46,
    47,
    48,
    49,
    50,
    51,
    52,
    53,
    54,
    55,
    56,
    57,
    58,
    59,
    60,
    61,
    62,
    63,
    64,
    65,
    66,
    67,
    68,
    69,
    70,
    71,
    72,
    73,
    74,
    75,
    76,
    77,
    78,
    79,
    80,
    81,
    82,
    83,
    84,
    85,
    86,
    87,
    88,
    89,
    90,
    91,
    92,
    93,
    94,
    95,
    96,
    97,
    98,
    99,
    100,
    101,
    102,
    103,
    104,
    105,
    106,
    107,
    108,
    109,
    110,
    111,
    112,
    113,
    114,
    115,
    116,
    117,
    118,
    119,
    120,
    121,
    122,
    123,
    124,
    125,
    126,
    127,
    128,
    129,
    130,
    131,
    132,
    133,
    134,
    135,
    136,
    137,
    138,
    139,
    140,
    141,
    142,
    143,
    144,
    145,
    146,
    147,
    148,
    149,
    150,
    151,
    152,
    153,
    154,
    155,
    156,
    157,
    158,
    159,
    160,
    161,
    162,
    163,
    164,
    165,
    166,
    167,
    168,
    169,
    170,
    171,
    172,
    173,
    174,
    175,
    176,
    177,
    178,
    179,
    180,
    181,
    182,
    183,
    184,
    185,
    186,
    187,
    188,
    189,
    190,
    191,
    192,
    193,
    194,
    195,
    196,
    197,
    198,
    199,
    200,
    201,
    202,
    203,
    204,
    205,
    206,
    207,
    208,
    209,
    210,
    211,
    212,
    213,
    214,
    215,
    216,
    217,
    218,
    219,
    220,
    221,
    222,
    223,
    224,
    225,
    226,
    227,
    228,
    229,
    230,
    231,
    232,
    233,
    234,
    235,
    236,
    237,
    238,
    239,
    240,
    241,
    242,
    243,
    244,
    245,
    246,
    247,
    248,
    249,
    250,
    251,
    252,
    253,
    254,
    255,
    256,
    257,
    258,
    259,
    260,
    261,
    262,
    263,
    264,
    265,
    266,
    267,
    268,
    269,
    270,
    271,
    272,
    273,
    274,
    275,
    276,
    277,
    278,
    279,
    280,
    281,
    282,
    283,
    284,
    285,
    286,
    287,
    288,
    289,
    290,
    291,
    292,
    293,
    294,
    295,
    296,
    297,
    298,
    299,
};

uint16_t DDRSS_phyRegNum[] = {
    0,
    1,
    2,
    3,
    4,
    5,
    6,
    7,
    8,
    9,
    10,
    11,
    12,
    13,
    14,
    15,
    16,
    17,
    18,
    19,
    20,
    21,
    22,
    23,
    24,
    25,
    26,
    27,
    28,
    29,
    30,
    31,
    32,
    33,
    34,
    35,
    36,
    37,
    38,
    39,
    40,
    41,
    42,
    43,
    44,
    45,
    46,
    47,
    48,
    49,
    50,
    51,
    52,
    53,
    54,
    55,
    56,
    57,
    58,
    59,
    60,
    61,
    62,
    63,
    64,
    65,
    66,
    67,
    68,
    69,
    70,
    71,
    72,
    73,
    74,
    75,
    76,
    77,
    78,
    79,
    80,
    81,
    82,
    83,
    84,
    85,
    86,
    87,
    88,
    89,
    90,
    91,
    92,
    93,
    94,
    95,
    96,
    97,
    98,
    99,
    100,
    101,
    102,
    103,
    104,
    105,
    106,
    107,
    108,
    109,
    110,
    111,
    112,
    113,
    114,
    115,
    116,
    117,
    118,
    119,
    120,
    121,
    122,
    123,
    124,
    125,
    126,
    127,
    128,
    129,
    130,
    131,
    132,
    133,
    134,
    135,
    136,
    137,
    138,
    139,
    140,
    141,
    142,
    143,
    144,
    145,
    146,
    147,
    148,
    149,
    150,
    151,
    152,
    153,
    154,
    155,
    156,
    157,
    158,
    159,
    160,
    161,
    162,
    163,
    164,
    165,
    166,
    167,
    168,
    169,
    170,
    171,
    172,
    173,
    174,
    175,
    176,
    177,
    178,
    179,
    180,
    181,
    182,
    183,
    184,
    185,
    186,
    187,
    188,
    189,
    190,
    191,
    192,
    193,
    194,
    195,
    196,
    197,
    198,
    199,
    200,
    201,
    202,
    203,
    204,
    205,
    206,
    207,
    208,
    209,
    210,
    211,
    212,
    213,
    214,
    215,
    216,
    217,
    218,
    219,
    220,
    221,
    222,
    223,
    224,
    225,
    226,
    227,
    228,
    229,
    230,
    231,
    232,
    233,
    234,
    235,
    236,
    237,
    238,
    239,
    240,
    241,
    242,
    243,
    244,
    245,
    246,
    247,
    248,
    249,
    250,
    251,
    252,
    253,
    254,
    255,
    256,
    257,
    258,
    259,
    260,
    261,
    262,
    263,
    264,
    265,
    266,
    267,
    268,
    269,
    270,
    271,
    272,
    273,
    274,
    275,
    276,
    277,
    278,
    279,
    280,
    281,
    282,
    283,
    284,
    285,
    286,
    287,
    288,
    289,
    290,
    291,
    292,
    293,
    294,
    295,
    296,
    297,
    298,
    299,
    300,
    301,
    302,
    303,
    304,
    305,
    306,
    307,
    308,
    309,
    310,
    311,
    312,
    313,
    314,
    315,
    316,
    317,
    318,
    319,
    320,
    321,
    322,
    323,
    324,
    325,
    326,
    327,
    328,
    329,
    330,
    331,
    332,
    333,
    334,
    335,
    336,
    337,
    338,
    339,
    340,
    341,
    342,
    343,
    344,
    345,
    346,
    347,
    348,
    349,
    350,
    351,
    352,
    353,
    354,
    355,
    356,
    357,
    358,
    359,
    360,
    361,
    362,
    363,
    364,
    365,
    366,
    367,
    368,
    369,
    370,
    371,
    372,
    373,
    374,
    375,
    376,
    377,
    378,
    379,
    380,
    381,
    382,
    383,
    384,
    385,
    386,
    387,
    388,
    389,
    390,
    391,
    392,
    393,
    394,
    395,
    396,
    397,
    398,
    399,
    400,
    401,
    402,
    403,
    404,
    405,
    406,
    407,
    408,
    409,
    410,
    411,
    412,
    413,
    414,
    415,
    416,
    417,
    418,
    419,
    420,
    421,
    422,
    423,
    424,
    425,
    426,
    427,
    428,
    429,
    430,
    431,
    432,
    433,
    434,
    435,
    436,
    437,
    438,
    439,
    440,
    441,
    442,
    443,
    444,
    445,
    446,
    447,
    448,
    449,
    450,
    451,
    452,
    453,
    454,
    455,
    456,
    457,
    458,
    459,
    460,
    461,
    462,
    463,
    464,
    465,
    466,
    467,
    468,
    469,
    470,
    471,
    472,
    473,
    474,
    475,
    476,
    477,
    478,
    479,
    480,
    481,
    482,
    483,
    484,
    485,
    486,
    487,
    488,
    489,
    490,
    491,
    492,
    493,
    494,
    495,
    496,
    497,
    498,
    499,
    500,
    501,
    502,
    503,
    504,
    505,
    506,
    507,
    508,
    509,
    510,
    511,
    512,
    513,
    514,
    515,
    516,
    517,
    518,
    519,
    520,
    521,
    522,
    523,
    524,
    525,
    526,
    527,
    528,
    529,
    530,
    531,
    532,
    533,
    534,
    535,
    536,
    537,
    538,
    539,
    540,
    541,
    542,
    543,
    544,
    545,
    546,
    547,
    548,
    549,
    550,
    551,
    552,
    553,
    554,
    555,
    556,
    557,
    558,
    559,
    560,
    561,
    562,
    563,
    564,
    565,
    566,
    567,
    568,
    569,
    570,
    571,
    572,
    573,
    574,
    575,
    576,
    577,
    578,
    579,
    580,
    581,
    582,
    583,
    584,
    585,
    586,
    587,
    588,
    589,
    590,
    591,
    592,
    593,
    594,
    595,
    596,
    597,
    598,
    599,
    600,
    601,
    602,
    603,
    604,
    605,
    606,
    607,
    608,
    609,
    610,
    611,
    612,
    613,
    614,
    615,
    616,
    617,
    618,
    619,
    620,
    621,
    622,
    623,
    624,
    625,
    626,
    627,
    628,
    629,
    630,
    631,
    632,
    633,
    634,
    635,
    636,
    637,
    638,
    639,
    640,
    641,
    642,
    643,
    644,
    645,
    646,
    647,
    648,
    649,
    650,
    651,
    652,
    653,
    654,
    655,
    656,
    657,
    658,
    659,
    660,
    661,
    662,
    663,
    664,
    665,
    666,
    667,
    668,
    669,
    670,
    671,
    672,
    673,
    674,
    675,
    676,
    677,
    678,
    679,
    680,
    681,
    682,
    683,
    684,
    685,
    686,
    687,
    688,
    689,
    690,
    691,
    692,
    693,
    694,
    695,
    696,
    697,
    698,
    699,
    700,
    701,
    702,
    703,
    704,
    705,
    706,
    707,
    708,
    709,
    710,
    711,
    712,
    713,
    714,
    715,
    716,
    717,
    718,
    719,
    720,
    721,
    722,
    723,
    724,
    725,
    726,
    727,
    728,
    729,
    730,
    731,
    732,
    733,
    734,
    735,
    736,
    737,
    738,
    739,
    740,
    741,
    742,
    743,
    744,
    745,
    746,
    747,
    748,
    749,
    750,
    751,
    752,
    753,
    754,
    755,
    756,
    757,
    758,
    759,
    760,
    761,
    762,
    763,
    764,
    765,
    766,
    767,
    768,
    769,
    770,
    771,
    772,
    773,
    774,
    775,
    776,
    777,
    778,
    779,
    780,
    781,
    782,
    783,
    784,
    785,
    786,
    787,
    788,
    789,
    790,
    791,
    792,
    793,
    794,
    795,
    796,
    797,
    798,
    799,
    800,
    801,
    802,
    803,
    804,
    805,
    806,
    807,
    808,
    809,
    810,
    811,
    812,
    813,
    814,
    815,
    816,
    817,
    818,
    819,
    820,
    821,
    822,
    823,
    824,
    825,
    826,
    827,
    828,
    829,
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};

0 Daviel Almonte over 1 year ago in reply to Daviel Almonte

TI__Expert 3285 points

When the SBL with the updated OSPI manufacture ID, there are no debug logs.

0 Parth Nagpal over 1 year ago in reply to Daviel Almonte

TI__Mastermind 42135 points

Hi Daviel,

Thanks for the details, can you please share the flash data sheet as well.

Please check this FAQ containing the guidelines for adding the new flash in PDK and make sure all the things have been taken care of.
Apart from Manufacturer ID and Device ID I believe you should also check if there is any change in command and dummy cycles which needs to be added, also please update the sizes as well.

Most probably the Board_flashOpen is failing because of device ID and manufacturer ID mismatch. Can you please check and share what IDs you are reading and what is the expected ID vlaues.

Regards,
Parth

0 Arumugam Elumalai over 1 year ago in reply to Parth Nagpal

Intellectual 365 points

The device ID and Vendor ID changed code also tried. After loading the changed one, we didn't see anything in UART log. But in the code, the memory size is not changed. Requested the modified code with right memory size, device ID and vendor ID.

0 Praveena Tallam over 1 year ago in reply to Arumugam Elumalai

Prodigy 60 points

We tried to keep SOC in UART Boot mode configuration, we expected to receive "C" on selected UART port but did not observe any data.

0 Daviel Almonte over 1 year ago in reply to Arumugam Elumalai

TI__Expert 3285 points

Hi Parth, I added the changes from the FAQ. Also the MT35XU02GCBA1G12 part is not out and is under NDA. do we have this datasheet internally that we can reference?

on the HW side, setting these pins to 000 is correct?

0 Praveena Tallam over 1 year ago in reply to Praveena Tallam

Prodigy 60 points

UART Boot mode configuration setting is working now, we are able to see "C" on selected UART.

0 Parth Nagpal over 1 year ago in reply to Praveena Tallam

TI__Mastermind 42135 points

Hi Daviel,

Daviel Almonte said:
Hi Parth, I added the changes from the FAQ. Also the MT35XU02GCBA1G12 part is not out and is under NDA. do we have this datasheet internally that we can reference?

Are you not getting any logs at all. At least you should get the SBL banner even if the OSPI fails. Can you please attach to CCS and check if the SBL is loaded properly or not? Please refer to the FAQ for reference: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1121933/faq-tda4vm-debugging-sbl-boot-in-rtos-sdk?tisearch=e2e-sitesearch&keymatch=faq%3Atrue

Regards,
Parth

0 Daviel Almonte over 1 year ago in reply to Parth Nagpal

TI__Expert 3285 points

Parth Nagpal said:
At least you should get the SBL banner even if the OSPI fails

I find this odd too. I am having trouble connecting through CCS, it will not connect to a target. also, when I test the debugger connection, it connot detect the EMU pins. can this possibly be the issue?

In Parallel these are my next steps.

1. Attempt to boot over UART. I built the UART SBL to be set over XMODEM.

2. Adjust ospi clock frequency to 45MHz. I see that it is being set to 133MHz from the OSPI_MODULE_CLK_133M definition. Would I redefine this variable?

0 Arumugam Elumalai over 1 year ago in reply to Daviel Almonte

Intellectual 365 points

Hi Daviel and Parth, we are able to log the SBL fail log when the file loaded without changing vendor and device ID. But after changing the vendor ID and device ID this is not working.

0 Daviel Almonte over 1 year ago in reply to Arumugam Elumalai

TI__Expert 3285 points

Update

1. Attempt to boot over UART. I built the UART SBL to be set over XMODEM.

- We were able to upload the UART_SBL though XMODEM. When we load the TIFS, there are no logs.

- Another note, this is a TDA4VM88TRBALFQ1. So we used this TIFS: tifs_sr1.1-hs-enc.bin, tifs-hs-enc.bin, tifs_sr2-hs-fs-enc.bin. and Nothing.

This is the UART string:

02000000011a00006a376573000000000000000048534653010101000101010002a6010000000000aa1f8e3095042e5c71ac40ede5b4e8c85fa87e03305ae0ea4f47933e89f4164aeb5a12ae13778f49de0622c1a578e6e747981d8c44a130f89a336a887a7955eead0bc40b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000cf0a500fcd1ecfcc88ebf9c2f37d79621616f75bcf50f32963f672c76cfa5f66CC

2. Reattempt Flashing the OSPI (this time we shared the file over Sharepoint instead of email)

- Banner now shows but same error "Board_flashOpen failed"

0 Suman Anna over 1 year ago in reply to Daviel Almonte

TI__Guru** 112775 points

Hi Daviel,

Daviel Almonte said:
- Another note, this is a TDA4VM88TRBALFQ1. So we used this TIFS: tifs_sr1.1-hs-enc.bin, tifs-hs-enc.bin, tifs_sr2-hs-fs-enc.bin. and Nothing.

If you are using pre-packaged HS-FS binaries from SDK 8.6, they are generated incorrectly.

The HS-FS binary should be a concatenation of the certificate and the encrypted TIFS binary. The pre-packaged HS-FS TIFS binary tifs_sr2-hs-fs-enc.bin in <ti-processor-sdk-rtos-j721e-evm-08_06_01_03>/pdk_jacinto_08_06_01_03/packages/ti/drv/sciclient/soc/V1 is double-signed like a HS-SE binary by mistake. So, please pick up the following commit on top of the 8.6 SDK that generates the proper HS-FS binary,

https://git.ti.com/gitweb?p=processor-sdk/pdk.git;a=commit;h=76d697ce7a2b6f83db3ecbe3a07e095fedf51926

A quick tell is the size of the binary w.r.t tifs_sr2-hs-enc.bin. The HS-FS binary will have one less certificate, so should be smaller in size.

regards

Suman

0 Daviel Almonte over 1 year ago in reply to Suman Anna

TI__Expert 3285 points

Hi Suman,

I am using SDK 9.0. and I attempted to use tifs_sr2-hs-enc.bin. but my understanding is that this is for the silicon revision 2, but this device is rev1.1.

I will update the SDK with the commit you provided but will it work for 9.0?

0 Karan Saxena over 1 year ago in reply to Daviel Almonte

TI__Guru* 77854 points

Daviel

For J721E SR1.1 HS-FS on SDK9.0 you can try the below image.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/tifs_5F00_sr1.1_2D00_hs_2D00_fs_2D00_enc.bin

I generated this by adding the below two image from bitbucket.itg.ti.com/.../ to sdk9_0/ti-processor-sdk-rtos-j721e-evm-09_00_00_02/pdk_jacinto_09_00_00_45/packages/ti/drv/sciclient/soc/sysfw/binaries

ti-fs-firmware-j721e_sr1_1-hs-fs-cert.bin

ti-fs-firmware-j721e_sr1_1-hs-fs-enc.bin

and then running the script firmwareHeaderGen.sh as below.

./firmwareHeaderGen.sh j721e_sr1_1-hs-fs

Regards

Karan

0 Praveena Tallam over 1 year ago in reply to Karan Saxena

Prodigy 60 points

HI Karan,

Thanks.

We tried in UART Boot mode configuration, looks like TDA is booting, here is the Boot log, please review.

We tried in OSPI boot mode also but ended up with the following error message.

SBL Revision: 01.00.10.01 (Oct 25 2023 - 22:20:26)
Board_flashOpen failed in SBL_ReadSysfwImage

The following is the procedure we followed for OSPI boot mode.

First, we flashed flash device (MT35XU02GCBA1G12-0AUT) with dediprog programmer.

sbl_ospi_img_mcu1_0_release.tiimage file at flash location 0x0
tifs_sr1.1-hs-fs-enc.bin file at flash location 0x80000

Next, we powered ON the module in OSPI boot mode and checked boot log on MCU_UART.

0 Parth Nagpal over 1 year ago in reply to Praveena Tallam

TI__Mastermind 42135 points

Hi,

Praveena Tallam said:
Board_flashOpen failed in SBL_ReadSysfwImage

Can you please check what manufacturer ID and what device ID is being read? Also, please share the expected device and manufacturer IDs

Regards,
Parth

0 Arumugam Elumalai over 1 year ago in reply to Parth Nagpal

Intellectual 365 points

MT35XU02GCBA1G12-0AUT--Flash PN.

Highlighted one is the actual part.

0 Daviel Almonte over 1 year ago in reply to Arumugam Elumalai

TI__Expert 3285 points

Hi,

We began running tests on the board to verify that the OSPI drivers work. when running the udma_baremetal_ospi_flash_testapp with the correct manufacturer ID and device ID. we get en error. I added some prints to catch the error and it shows that the " OspiFlash_ospiOpen()" function passes. but fails on "OspiFlash_ospiConfigPHY(clk, FALSE)".

Src code used: udma_ospi_flash_test.c

/*
 *  Copyright (c) Texas Instruments Incorporated 2020 - 2022
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/**
 *  \file udma_ospi_flash_test.c
 *
 *  \brief UDMA OSPI Flash sample application performs DAC DMA mode ospi write and read 
 *  at 133MHz RCLK and 166MHz RCLK with UDMA 3D transfer using SW trigger method as below.
 * 
 *  Performs OSPI write of "appTestObj->numBytes" bytes:
 *      - Loop L times (icnt1)
 *         - SW trigger UDMA Channel -> Triggers OSPI Write of K bytes from R5 TCM to OSPI Data Buffer
 *         - wait for transfer to complete
 *         - wait for ospi flash to get ready for next write
 *  > Eack inner loop writes K (inct0) bytes of data and wait for device to be ready.
 *  > R5 TCM and OSPI Data Buffer size is L x K bytes.
 * 
 *  Where,
 *      - K is icnt0 - "UDMA_TEST_WRITE_CHUNK_SIZE"
 *      - L is icnt1 - is chunkCnt: "appTestObj->numBytes/UDMA_TEST_WRITE_CHUNK_SIZE"
 * 
 *  Performs OSPI read of "appTestObj->numBytes" bytes, UDMA_TEST_XFER_REPEAT_CNT no. of times
 *     - Loop N times:
 *          [The following performs OSPI read of icnt0 bytes]
 *          - SW trigger UDMA Channel -> Triggers OSPI Read M bytes from OSPI Data Buffer to R5 TCM 
 *          - Wait for transfer to complete
 * 
 *  > Each loop transfers M (icnt0) bytes of data
 *  > R5 TCM and OSPI Data Buffer size is M bytes.
 *  > For each loop the tranfer restarts from the origin address.
 *
 *  Where,
 *      - M is icnt0 - "appTestObj->numBytes"  
 *          This refers to the no. of bytes transferred per OSPI Read operation.
 *      - N is UDMA_TEST_XFER_REPEAT_CNT
 *         This parameters can be used to configure the the no.of times to repeat the whole transfer starting from the origin address.
 * 
 *  This read illustrates TR Reload Feature in which TR Reload count is set as 0x1FFU for perpetual loop.
 *  In this example, after UDMA_TEST_XFER_REPEAT_CNT no.of read operations, we teardown the channel to exit from the loop.
 * 
 *  Note: This application has minimal DMA setup to configure OSPI for a particular DAC read.
 *  Users need to make changes to this app if they want to test different OSPI or DMA configurations,
 *  refer to OSPI and UDMA drivers for the same.
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <stdio.h>
#include <ti/csl/soc.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/hw_types.h>
#include <ti/drv/udma/udma.h>
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/udma/examples/udma_apputils/udma_apputils.h>
#include <ti/csl/example/ospi/ospi_flash/common/ospi_flash_common.h>
#include <ti/csl/example/ospi/ospi_flash/common/ospi_flash_phy_tune.h>
#include <ti/csl/example/ospi/ospi_flash/common/ospi_flash_patterns.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/*
 * Flash type
 */
#if defined (SOC_J7200) || defined(SOC_AM64X) || (SOC_J721S2) || (SOC_J784S4)
#define FLASH_TYPE_XSPI
#else
#define FLASH_TYPE_OSPI
#endif

/*
 * Application test config parameters
 */
/** \brief Maximum Number of bytes to perform OSPI Read/Write per operation (Actual number based on test) */
#define UDMA_TEST_XFER_MAX_NUM_BYTES    (1024U)
/** \brief Number of times to repeat whole data tranfer */
#define UDMA_TEST_XFER_REPEAT_CNT       (10U)
/** \brief ChunkSize in bytes for each DMA mode OSPI Flash Write operation */
#define UDMA_TEST_WRITE_CHUNK_SIZE      (16U)
/** \brief Disable CacheOps in Realtime loop */
#define UDMA_TEST_DISABLE_RT_CACHEOPS

/*
 * Application other test parameters
 */

/** \brief Total number of bytes to copy and buffer allocation */
#define UDMA_TEST_APP_MAX_TOTAL_NUM_BYTES   (UDMA_TEST_XFER_MAX_NUM_BYTES)
/** \brief This ensures every channel memory is aligned */
#define UDMA_TEST_APP_BUF_SIZE_ALIGN        ((UDMA_TEST_APP_MAX_TOTAL_NUM_BYTES + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))

/*
 * Ring parameters
 */
/** \brief Number of ring entries - we can prime this much memcpy operations */
#define UDMA_TEST_APP_RING_ENTRIES      (1U)
/** \brief Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
#define UDMA_TEST_APP_RING_ENTRY_SIZE   (sizeof(uint64_t))
/** \brief Total ring memory */
#define UDMA_TEST_APP_RING_MEM_SIZE     (UDMA_TEST_APP_RING_ENTRIES * \
                                         UDMA_TEST_APP_RING_ENTRY_SIZE)
/** \brief This ensures every channel memory is aligned */
#define UDMA_TEST_APP_RING_MEM_SIZE_ALIGN ((UDMA_TEST_APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
/**
 *  \brief UDMA TR packet descriptor memory.
 *  This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
 *  one Type_15 TR (CSL_UdmapTR15) + one TR response of 4 bytes.
 *  Since CSL_UdmapCppi5TRPD is less than CSL_UdmapTR15, size is just two times
 *  CSL_UdmapTR15 for alignment.
 */
#define UDMA_TEST_APP_TRPD_SIZE         ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
/** \brief This ensures every channel memory is aligned */
#define UDMA_TEST_APP_TRPD_SIZE_ALIGN   ((UDMA_TEST_APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))

/*
 * UDMA OSPI Flash test ID definitions
 */
/** \brief OSPI flash test at 133MHz RCLK - Read/Write 16 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_16B     (0U)  
/** \brief OSPI flash test at 166MHz RCLK - Read/Write 16 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_16B     (1U) 
/** \brief OSPI flash test at 133MHz RCLK - Read/Write 32 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_32B     (2U) 
/** \brief OSPI flash test at 166MHz RCLK - Read/Write 32 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_32B     (3U)  
/** \brief OSPI flash test at 133MHz RCLK - Read/Write 64 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_64B     (4U)  
/** \brief OSPI flash test at 166MHz RCLK - Read/Write 64 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_64B     (5U)  
/** \brief OSPI flash test at 133MHz RCLK - Read/Write 128 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_128B    (6U) 
/** \brief OSPI flash test at 166MHz RCLK - Read/Write 128 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_128B    (7U)  
/** \brief OSPI flash test at 133MHz RCLK - Read/Write 256 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_256B    (8U)  
/** \brief OSPI flash test at 166MHz RCLK - Read/Write 256 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_256B    (9U)   
/** \brief OSPI flash test at 133MHz RCLK - Read/Write 512 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_512B    (10U)  
/** \brief OSPI flash test at 166MHz RCLK - Read/Write 512 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_512B    (11U)  
/** \brief OSPI flash test at 133MHz RCLK - Read/Write 1024 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_1024B   (12U) 
/** \brief OSPI flash test at 166MHz RCLK - Read/Write 1024 Bytes */
#define UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_1024B   (13U)
/** \brief OSPI flash test at 133MHz RCLK - Write PHY tuning data (For Cypress Flash)*/
#define UDMA_OSPI_FLASH_TEST_ID_WR_TUNING            (14U)

/** \brief Get GTC Timer Ticks */
#define App_getGTCTimerTicks() (*((uint64_t *)(CSL_GTC0_GTC_CFG1_BASE + 0x8U)))

/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */

typedef struct
{
    struct Udma_EventObj    trEventObj;

    Udma_EventHandle        trEventHandle;
    Udma_EventPrms          trEventPrms;

    /**< TR Reload Count */
    uint32_t                reloadCnt;

    uint32_t                trigger;
    /**< Global0 or Global 1 Trigger - refer \ref CSL_UdmapTrFlagsTrigger. */
    uint32_t                eventSize;
    /**< Refer \ref CSL_UdmapTrFlagsEventSize. */
    uint32_t                triggerType;
    /**< Refer \ref CSL_UdmapTrFlagsTriggerType. */
    uint32_t                eolType;
    /**< Refer \ref CSL_UdmapTrFlagsEol. */

    /**< Refer TR Address and Size Attributes */
    uint16_t                icnt[4];    
    uint16_t                dicnt[4];    
    int32_t                 dim[3];
    int32_t                 ddim[3];    
    uint8_t                *addr;    
    uint8_t                *daddr;    

    Udma_DrvHandle          drvHandle;

} App_UdmaTrObj;

typedef struct
{
    struct Udma_ChObj       chObj;
    App_UdmaTrObj           appTrObj;   

#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
    struct Udma_EventObj    tdCqEventObj;
    Udma_EventHandle        tdCqEventHandle;
    Udma_EventPrms          tdCqEventPrms;
#endif 

    Udma_ChHandle           chHandle;
    Udma_DrvHandle          drvHandle;

    uint8_t                 *txRingMem;
#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
    uint8_t                 *txCompRingMem;
    uint8_t                 *txTdCompRingMem;
#endif
    uint8_t                 *trpdMem;

} App_UdmaChObj;

typedef struct 
{
    int32_t  (*testFunc)(void);
    int32_t  testId;    
    uint32_t clk;
    uint32_t numBytes;
    char     testDesc[80];

} App_UdmaTestObj;

typedef struct
{
    /**< GTC Timer ticks at start of profiling OSPI write. */
    volatile uint64_t       txStartTicks;
    /**< GTC Timer ticks at stop of profiling OSPI write. */
    volatile uint64_t       txStopTicks;
    /**< Measured total no. of GTC Timer ticks for OSPI write. */
    volatile uint64_t       txTotalTicks;
    /**< Elapsed time in nsec for OSPI write.. */
    volatile uint64_t       txElapsedTime;

    /**< GTC Timer ticks at start of profiling OSPI read. */
    volatile uint64_t       rxStartTicks[UDMA_TEST_XFER_REPEAT_CNT];
    /**< GTC Timer ticks at stop of profiling OSPI read. */
    volatile uint64_t       rxStopTicks[UDMA_TEST_XFER_REPEAT_CNT];
    /**< Measured total no. of GTC Timer ticks for OSPI read. */
    volatile uint64_t       rxTotalTicks[UDMA_TEST_XFER_REPEAT_CNT + 1U];
    /**< Elapsed time in nsec for OSPI read. */
    volatile uint64_t       rxElapsedTime[UDMA_TEST_XFER_REPEAT_CNT + 1U];

} App_UdmaCounterObj;

typedef struct
{
    struct Udma_DrvObj      drvObj;
    App_UdmaChObj           appChObj;
    App_UdmaTestObj         appTestObj;
    App_UdmaCounterObj      appCounterObj;    
    uint32_t                totalNumBytes;
} App_UdmaObj;


/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

static int32_t Udma_ospiFlashTestRun(void);

static int32_t App_ospiFlashTest(App_UdmaObj *appObj, App_OspiObj *ospiObj);
static int32_t App_udmaOspiFlash(App_UdmaObj *appObj, App_OspiObj *ospiObj);
static int32_t App_udmaOspiFlashWrite(App_UdmaObj *appObj, App_OspiObj *ospiObj) __attribute__((section(".udma_critical_fxns")));
static int32_t App_udmaOspiFlashRead(App_UdmaObj *appObj) __attribute__((section(".udma_critical_fxns")));

#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
static void App_udmaEventTdCb(Udma_EventHandle eventHandle,
                              uint32_t eventType,
                              void *appData);
#endif

static int32_t App_init(App_UdmaObj *appObj, App_OspiObj *ospiObj);
static int32_t App_deinit(App_UdmaObj *appObj, App_OspiObj *ospiObj);

static int32_t App_create(App_UdmaObj *appObj);
static int32_t App_delete(App_UdmaObj *appObj);

static void App_udmaTrpdInit(App_UdmaTrObj *appTrObj, App_UdmaChObj  *appChObj);
#if defined(FLASH_TYPE_OSPI)
static int32_t App_udmaTrpdSanityCheck(App_UdmaChObj *appChObj, uint64_t pDesc);
static inline void App_udmaTrObjInitWrite(App_UdmaTestObj *appTestObj, App_UdmaTrObj *appTrObj);
#endif
static inline void App_udmaTrObjInitRead(App_UdmaTestObj *appTestObj, App_UdmaTrObj *appTrObj);

static void App_printPerfResults(App_UdmaObj *appObj);

void App_print(const char *str);
static void App_printNum(const char *str, uint32_t num);
int32_t App_setGTCClk(uint32_t moduleId,
                      uint32_t clkId,
                      uint64_t clkRateHz);


static int32_t App_ospiFlashInit(App_OspiObj *ospiObj, uint32_t clk);
void App_ospiFlashConfigDacMode( App_OspiObj *ospiObj, bool dacMode);
#if defined(FLASH_TYPE_OSPI)
static int32_t App_ospiFlashStart(uint32_t numBytes) __attribute__((section(".udma_critical_fxns")));
#endif

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/*
 * UDMA driver and channel objects
 */
App_UdmaObj gUdmaAppObj;
App_OspiObj gOspiAppObj;

/*
 * UDMA Memories
 */
static uint8_t gTxRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT), section(".udma_buffer_r5_tcm")));
#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
static uint8_t gTxCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT), section(".udma_buffer_r5_tcm")));
static uint8_t gTxTdCompRingMem[UDMA_TEST_APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT), section(".udma_buffer_r5_tcm")));
#endif
static uint8_t gUdmaTrpdMem[UDMA_TEST_APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

/*
 * Application Buffers
 */
static uint8_t gUdmaTestTxBuf[UDMA_TEST_APP_BUF_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT), section(".udma_buffer_r5_tcm")));
static uint8_t gUdmaTestRxBuf[UDMA_TEST_APP_BUF_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT), section(".udma_buffer_r5_tcm")));
static uint8_t * gUdmaTestOspiFlashDataAddr = (uint8_t *)(OSPI_FLASH_DATA_BASE_ADDR);

/* Global test pass/fail flag */
static volatile int32_t gUdmaTestResult = UDMA_SOK;
/* Global App pass/fail flag */
static volatile int32_t gUdmaAppResult = UDMA_SOK;

/* UDMA OSPI Flash Tests data structure */
App_UdmaTestObj gUdmaAppTestObj[] =
{
    /* testFunc, testID, clk, numBytes, testDesc */
#if defined(FLASH_TYPE_XSPI)
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_WR_TUNING,         OSPI_MODULE_CLK_133M, OSPI_FLASH_ATTACK_VECTOR_SIZE, "\r\n OSPI flash test at 133MHz RCLK - Write PHY tuning data"},
#endif
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_16B,  OSPI_MODULE_CLK_133M, 16U, "\r\n OSPI flash test at 133MHz RCLK - Read/Write 16 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_16B,  OSPI_MODULE_CLK_166M, 16U, "\r\n OSPI flash test at 166MHz RCLK - Read/Write 16 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_32B,  OSPI_MODULE_CLK_133M, 32U, "\r\n OSPI flash test at 133MHz RCLK - Read/Write 32 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_32B,  OSPI_MODULE_CLK_166M, 32U, "\r\n OSPI flash test at 166MHz RCLK - Read/Write 32 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_64B,  OSPI_MODULE_CLK_133M, 64U, "\r\n OSPI flash test at 133MHz RCLK - Read/Write 64 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_64B,  OSPI_MODULE_CLK_166M, 64U, "\r\n OSPI flash test at 166MHz RCLK - Read/Write 64 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_128B,  OSPI_MODULE_CLK_133M, 128U, "\r\n OSPI flash test at 133MHz RCLK - Read/Write 128 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_128B,  OSPI_MODULE_CLK_166M, 128U, "\r\n OSPI flash test at 166MHz RCLK - Read/Write 128 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_256B,  OSPI_MODULE_CLK_133M, 256U, "\r\n OSPI flash test at 133MHz RCLK - Read/Write 256 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_256B,  OSPI_MODULE_CLK_166M, 256U, "\r\n OSPI flash test at 166MHz RCLK - Read/Write 256 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_512B,  OSPI_MODULE_CLK_133M, 512U, "\r\n OSPI flash test at 133MHz RCLK - Read/Write 512 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_512B,  OSPI_MODULE_CLK_166M, 512U, "\r\n OSPI flash test at 166MHz RCLK - Read/Write 512 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_133M_1024B,  OSPI_MODULE_CLK_133M, 1024U, "\r\n OSPI flash test at 133MHz RCLK - Read/Write 1024 Bytes"},
    {Udma_ospiFlashTestRun, UDMA_OSPI_FLASH_TEST_ID_DAC_DMA_166M_1024B,  OSPI_MODULE_CLK_166M, 1024U, "\r\n OSPI flash test at 166MHz RCLK - Read/Write 1024 Bytes"},
    {NULL, }
};

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

/*
 * UDMA OSPI Flash test
 */
int32_t Udma_ospiFlashTest(void)
{
    int32_t          retVal;
    uint32_t         i;
    App_UdmaTestObj *test;
    App_UdmaObj     *appObj = &gUdmaAppObj;

    for (i = 0; ; i++)
    {
        test = &gUdmaAppTestObj[i];
        if (test->testFunc == NULL)
        {
            break;
        }

        appObj->appTestObj = *test;
        appObj->totalNumBytes = test->numBytes;
        retVal = test->testFunc();
        if((UDMA_SOK == retVal) && (UDMA_SOK == gUdmaTestResult))
        {
            App_print(test->testDesc);
            App_print(" have passed\r\n");
        }
        else
        {
            App_print(test->testDesc);
            App_print(" have failed\r\n");
            gUdmaTestResult = UDMA_SOK;
            gUdmaAppResult = UDMA_EFAIL;
        }
    }

    if(UDMA_SOK != gUdmaAppResult)
    {
        App_print("\n Some tests have failed. \n");
    }
    else
    {
        App_print("\n All tests have passed. \n");
    }

    App_print("\n Done\n");

    return (0);
}

/*
 * UDMA OSPI Flash test run
 */
static int32_t Udma_ospiFlashTestRun(void)
{
    int32_t         retVal;
    App_UdmaObj    *appObj = &gUdmaAppObj;
    App_OspiObj    *ospiObj = &gOspiAppObj;

    retVal = App_init(appObj, ospiObj);
    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] UDMA App init failed!!\n");
    }

    App_print("UDMA OSPI Flash application started...\n");

    if(UDMA_SOK == retVal)
    {
        retVal = App_create(appObj);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA App create failed!!\n");
        }
    }

    if(UDMA_SOK == retVal)
    {
        retVal = App_ospiFlashTest(appObj, ospiObj);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA App OSPI Flash test failed!!\n");
        }
    }

    retVal += App_delete(appObj);
    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] UDMA App delete failed!!\n");
    }

    retVal += App_deinit(appObj, ospiObj);
    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] UDMA App deinit failed!!\n");
    }

    return (retVal);
}

static int32_t App_ospiFlashTest(App_UdmaObj *appObj, App_OspiObj *ospiObj)
{
    int32_t         retVal = UDMA_SOK;
    uint32_t        i;
    uint8_t        *rxBuf;

    /* Reset RX buffer */
    rxBuf  = &gUdmaTestRxBuf[0U];
    for(i = 0U; i < appObj->totalNumBytes; i++)
    {
        rxBuf[i] = 0U;
    }
    /* Writeback RX buffer */
    Udma_appUtilsCacheWb(rxBuf, appObj->totalNumBytes);

    /* Perform UDMA memcpy */
    retVal = App_udmaOspiFlash(appObj, ospiObj);
    if(UDMA_SOK == retVal)
    {
        /* Print performance results for OSPI Flash in DAC DMA mode */
        App_printPerfResults(appObj);
    }

    return (retVal);
}

static int32_t App_udmaOspiFlash(App_UdmaObj *appObj, App_OspiObj *ospiObj)
{
    int32_t         retVal = UDMA_SOK;
    App_UdmaTestObj *appTestObj = &appObj->appTestObj;
    uint32_t        i;
    uint8_t        *rxBuf, *txBuf;

#if defined(FLASH_TYPE_OSPI)
    retVal = App_ospiFlashStart(appObj->totalNumBytes);
    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] OSPI Start failed!!\n");
    }
#endif

    if(UDMA_SOK == retVal)
    {
        retVal = App_udmaOspiFlashWrite(appObj, ospiObj);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error]UDMA OSPI Write failed!!\n");
        }
    #if defined(FLASH_TYPE_XSPI)
        /* For XSPI Flash App_ospiFlashInit configures in INDAC mode for Write.
         * Now switching to DAC mode to perform DAC DMA read.
         */
        App_ospiFlashConfigDacMode(ospiObj, TRUE);
    #endif
    }

    if(UDMA_SOK == retVal)
    {
        retVal = App_udmaOspiFlashRead(appObj);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error]UDMA OSPI Read failed!!\n");
        }
    }

    if(appTestObj->testId != UDMA_OSPI_FLASH_TEST_ID_WR_TUNING)
    {
        if(UDMA_SOK == retVal)
        {
            rxBuf  = &gUdmaTestRxBuf[0U];
            txBuf  = &gUdmaTestTxBuf[0U];

#ifdef UDMA_TEST_DISABLE_RT_CACHEOPS
            /* Invalidate destination buffer */
            Udma_appUtilsCacheInv(rxBuf, appObj->totalNumBytes);
#endif
            /* Compare data */
            for(i = 0U; i < appObj->totalNumBytes; i++)
            {
                if(rxBuf[i] != txBuf[i])
                {
                    App_printNum("\n [Error] Data mismatch at idx %d", i);
                    retVal = UDMA_EFAIL;
                    break;
                }
            }
        }
    }

    return (retVal);
}

/* Micron OSPI Flash supports writes in DAC Mode */
#if defined(FLASH_TYPE_OSPI)
static int32_t App_udmaOspiFlashWrite(App_UdmaObj *appObj, App_OspiObj *ospiObj)
{
    int32_t              retVal = UDMA_SOK;
    uint64_t             pDesc = 0;
    uint32_t             i;
    uint32_t             chunkCnt, cCnt;
    /* Use local variables in real-time loop for optimized performance */
    uint32_t             txStartTicks, txStopTicks;
    volatile uint32_t   *pSwTriggerReg;
    uint32_t             triggerMask;
    App_UdmaTestObj     *appTestObj       = &appObj->appTestObj;
    App_UdmaChObj       *appChObj         = &appObj->appChObj;
    App_UdmaTrObj       *appTrObj         = &appChObj->appTrObj;
    App_UdmaCounterObj  *appCounterObj    = &appObj->appCounterObj;
    Udma_ChHandle        chHandle         = appChObj->chHandle;
    uint8_t             *txBuf            = &gUdmaTestTxBuf[0U];
    const uint16_t       size             = appTestObj->numBytes;
    const uint16_t       totalSize        = appObj->totalNumBytes;
    volatile uint64_t   *pintrStatusReg   = appTrObj->trEventPrms.intrStatusReg;
    uint64_t             intrMask         = appTrObj->trEventPrms.intrMask;
    volatile uint64_t   *intrClearReg     = appTrObj->trEventPrms.intrClearReg;
    uint8_t             *trpdMem          = appChObj->trpdMem;

    const CSL_ospi_flash_cfgRegs *baseAddr = (const CSL_ospi_flash_cfgRegs *)(OSPI_FLASH_CONFIG_REG_BASE_ADDR);

    /* Init TX buffers */
    for(i = 0U; i < totalSize; i++)
    {
        txBuf[i] = i;
    }
    
    App_udmaTrObjInitWrite(appTestObj, appTrObj);

    /* Get SW trigger register for easy access */
    triggerMask = ((uint32_t)1U << (appTrObj->trigger - 1U));
    pSwTriggerReg = (volatile uint32_t *) Udma_chGetSwTriggerRegister(chHandle);
    if(NULL == pSwTriggerReg)
    {
        App_print("\n [Error] Channel trigger register get failed!!\n");
    }

    /* Submit TRPD to channels */
    App_udmaTrpdInit(appTrObj, appChObj);
    retVal = Udma_ringQueueRaw(
                Udma_chGetFqRingHandle(chHandle),
                (uint64_t) Udma_appVirtToPhyFxn(trpdMem, 0U, NULL));
    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] Channel queue failed!!\n");
    }

    if(UDMA_SOK == retVal)
    {

        /*****************************************************************************
         * OSPI Write "appTestObj->numBytes" (= appTrObj->icnt[0]* appTrObj->icnt[1] )
         *****************************************************************************/
        txStartTicks = App_getGTCTimerTicks();

        /* Do Cache write-back for "appTestObj->numBytes" chunk to be tranferred */
        CSL_armR5CacheWb(txBuf, size, (bool)TRUE);
        
        /* Set number of times to trigger TX transfer */
        chunkCnt = appTrObj->icnt[1];
        for(cCnt = 0U; cCnt < chunkCnt; cCnt++)
        {
            /* Write UDMA_TEST_WRITE_CHUNK_SIZE(= appTrObj->icnt[0]) bytes and wait for device to be ready */

            /* Set channel trigger and wait for completion */
            CSL_REG32_WR(pSwTriggerReg, triggerMask);

            /* Wait for the transfer to complete in polling mode */
            while(1U)
            {
                volatile uint64_t   intrStatusReg;
                intrStatusReg = CSL_REG64_RD(pintrStatusReg);
                /* Check whether the interrupt status Reg is set - which indicates the
                * tranfser completion of appTestObj->numBytes */
                if(intrStatusReg & intrMask)
                {
                    /* Clear interrupt */
                    CSL_REG64_WR(intrClearReg, intrMask);
                    break;
                }
            }

            /* Wait device to be ready after write operation */
            uint32_t timeOutVal = OSPI_FLASH_WRITE_TIMEOUT;
            uint32_t retry = OSPI_FLASH_WRITE_TIMEOUT;
            volatile uint32_t delay = OSPI_FLASH_CHECK_IDLE_DELAY;
            uint8_t  status = 0xFF;
            uint32_t regVal;
            while (timeOutVal != 0U)
            {
                (void)CSL_ospiCmdRead(baseAddr, OSPI_FLASH_CMD_RDSR, 1U);
                while(!CSL_ospiIsIdle(baseAddr));
                CSL_ospiFlashExecCmd(baseAddr);
                while(retry != 0U)
                {
                    if(CSL_ospiFlashExecCmdComplete(baseAddr) == TRUE)
                    {
                        break;
                    }
                    while (delay > 0U)
                    {  
                        delay = delay - 1U;
                    }
                    retry--;
                }
                while(!CSL_ospiIsIdle(baseAddr));
                regVal = CSL_REG32_RD(&baseAddr->FLASH_RD_DATA_LOWER_REG);
                (void)memcpy((void *)&status, (void *)(&regVal), 1U);
                if ((status & 1U) == 0U)
                {
                    break;
                }
                timeOutVal--;
                delay = OSPI_FLASH_CHECK_IDLE_DELAY;
                while (delay > 0U)
                {  
                    delay = delay - 1U;
                }
            }
        } 
        txStopTicks = App_getGTCTimerTicks();

        appCounterObj->txStartTicks = txStartTicks;
        appCounterObj->txStopTicks = txStopTicks;
        
    }
    if(UDMA_SOK == retVal)
    {
        /* wait for response to be received in completion queue */
        while(1)
        {
            retVal =
                Udma_ringDequeueRaw(Udma_chGetCqRingHandle(chHandle), &pDesc);
            if(UDMA_SOK == retVal)
            {
                break;
            }
        }

        /* Sanity check - Check returned descriptor pointer & TR response status*/
        retVal = App_udmaTrpdSanityCheck(appChObj, pDesc);
    }

    return (retVal);
}
#else
/* Cypress XSPI Flash does not support writes in DAC mode */
static int32_t App_udmaOspiFlashWrite(App_UdmaObj *appObj, App_OspiObj *ospiObj)
{
    int32_t              retVal = UDMA_SOK;
    uint32_t             i;
    /* Use local variables in real-time loop for optimized performance */
    uint32_t             txStartTicks, txStopTicks;
    App_UdmaCounterObj  *appCounterObj    = &appObj->appCounterObj;
    App_UdmaTestObj     *appTestObj       = &appObj->appTestObj;
    uint8_t             *txBuf            = &gUdmaTestTxBuf[0U];
    uint16_t             totalSize        = appObj->totalNumBytes;
    uint32_t             offset;

    /* Init TX buffers */
    if(appTestObj->testId == UDMA_OSPI_FLASH_TEST_ID_WR_TUNING)
    {
        for(i = 0U; i < totalSize; i++)
        {
            txBuf[i] = ospi_flash_attack_vector[i];
        }
        offset = OSPI_FLASH_TUNING_DATA_OFFSET;
    }
    else
    {
        for(i = 0U; i < totalSize; i++)
        {
            txBuf[i] = i;
        }
        offset = 0;
    }

    /* Capture the time at the beginning of operation */
    txStartTicks = App_getGTCTimerTicks();

    /* Call the API to write in INDAC mode */
    OspiFlash_xspiIndacWrite(ospiObj, txBuf, totalSize, FALSE, offset);

    /* Capture the time at the end of operation */
    txStopTicks = App_getGTCTimerTicks();

    /* Save the captured time to the app object */
    appCounterObj->txStartTicks = txStartTicks;
    appCounterObj->txStopTicks = txStopTicks;

    return (retVal);
}
#endif

static int32_t App_udmaOspiFlashRead(App_UdmaObj *appObj)
{
    int32_t              retVal = UDMA_SOK;
    uint32_t             triggerCnt, tCnt;
    /* Use local variables in real-time loop for optimized performance */
    volatile uint32_t   *pSwTriggerReg;
    uint32_t             triggerMask;
    uint32_t             rxStartTicks, rxStopTicks;
    App_UdmaTestObj     *appTestObj       = &appObj->appTestObj;
    App_UdmaChObj       *appChObj         = &appObj->appChObj;
    App_UdmaTrObj       *appTrObj         = &appChObj->appTrObj;
    App_UdmaCounterObj  *appCounterObj    = &appObj->appCounterObj;
    Udma_ChHandle        chHandle         = appChObj->chHandle;
#ifndef UDMA_TEST_DISABLE_RT_CACHEOPS
    uint8_t             *rxBuf            = &gUdmaTestRxBuf[0U];
    const uint16_t       size             = appTestObj->numBytes;
#endif
    volatile uint64_t   *pintrStatusReg   = appTrObj->trEventPrms.intrStatusReg;
    uint64_t             intrMask         = appTrObj->trEventPrms.intrMask;
    volatile uint64_t   *intrClearReg     = appTrObj->trEventPrms.intrClearReg;
    uint8_t             *trpdMem          = appChObj->trpdMem;

    if(appTestObj->testId != UDMA_OSPI_FLASH_TEST_ID_WR_TUNING)
    {
    #if defined(FLASH_TYPE_XSPI)
        OspiFlash_spiPhyTune(TRUE, OSPI_FLASH_TUNING_DATA_OFFSET, appTestObj->clk);
    #endif

        App_udmaTrObjInitRead(appTestObj, appTrObj);

        /* Get SW trigger register for easy access */
        triggerMask = ((uint32_t)1U << (appTrObj->trigger - 1U));
        pSwTriggerReg = (volatile uint32_t *) Udma_chGetSwTriggerRegister(chHandle);
        if(NULL == pSwTriggerReg)
        {
            App_print("\n [Error] Channel trigger register get failed!!\n");
        }

        /* Submit TRPD to channels */
        App_udmaTrpdInit(appTrObj, appChObj);
        retVal = Udma_ringQueueRaw(
                    Udma_chGetFqRingHandle(chHandle),
                    (uint64_t) Udma_appVirtToPhyFxn(trpdMem, 0U, NULL));
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] Channel queue failed!!\n");
        }

        if(UDMA_SOK == retVal)
        {
            /* Set number of times to trigger RX transfer */
            triggerCnt = UDMA_TEST_XFER_REPEAT_CNT;
            for(tCnt = 0U; tCnt < triggerCnt; tCnt++)
            {      

                /********************************************************
                 * OSPI Read "appTestObj->numBytes" (= appTrObj->icnt[0])
                 ********************************************************/

                rxStartTicks = App_getGTCTimerTicks();

                /* Set channel trigger and wait for completion */
                CSL_REG32_WR(pSwTriggerReg, triggerMask);

                /* Wait for the transfer to complete in polling mode */
                while(1U)
                {
                    volatile uint64_t   intrStatusReg;
                    intrStatusReg = CSL_REG64_RD(pintrStatusReg);
                    /* Check whether the interrupt status Reg is set - which indicates the
                    * transfer completion of appTestObj->numBytes */
                    if(intrStatusReg & intrMask)
                    {
                        /* Clear interrupt */
                        CSL_REG64_WR(intrClearReg, intrMask);
                        break;
                    }
                }
#ifndef UDMA_TEST_DISABLE_RT_CACHEOPS
                /* Do Cache invalidate for the received chunk */
                CSL_armR5CacheInv(rxBuf, size, (bool)TRUE);
#endif

                rxStopTicks = App_getGTCTimerTicks();

                appCounterObj->rxStartTicks[tCnt] = rxStartTicks;
                appCounterObj->rxStopTicks[tCnt] = rxStopTicks;
            }
        }
        /* Since TR Reload Count Set for perpetual loop, TRPD never completes and comes back to CQ.
        * To exit, teardown the channel using Udma_chDisable */
        retVal = Udma_chDisable(chHandle, UDMA_DEFAULT_CH_DISABLE_TIMEOUT);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA channel disable failed!!\n");
        }
        /* During channel forced teardown to break from the TR Reload Perpetual loop,
         * DMA will complete the already reloaded TR. This results in setting the 
         * interrupt status register after this transfer completion.
         * Hence clear the interrupt */
        CSL_REG64_WR(intrClearReg, intrMask);
    }
    return (retVal);
}

#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
static void App_udmaEventTdCb(Udma_EventHandle eventHandle,
                              uint32_t eventType,
                              void *appData)
{
    int32_t             retVal;
    CSL_UdmapTdResponse tdResp;
    App_UdmaChObj      *appChObj = (App_UdmaChObj *) appData;

    if(appChObj != NULL)
    {
        if(UDMA_EVENT_TYPE_TEARDOWN_PACKET == eventType)
        {
            /* Response received in Teardown completion queue */
            retVal = Udma_chDequeueTdResponse(appChObj->chHandle, &tdResp);
            if(UDMA_SOK != retVal)
            {
                /* [Error] No TD response after callback!! */
                gUdmaTestResult = UDMA_EFAIL;
            }
        }
        else
        {
            gUdmaTestResult = UDMA_EFAIL;
        }
    }
    else
    {
        gUdmaTestResult = UDMA_EFAIL;
    }

    return;
}
#endif

static int32_t App_init(App_UdmaObj *appObj, App_OspiObj *ospiObj)
{
    int32_t              retVal;
    Udma_InitPrms        initPrms;
    uint32_t             instId;
    App_UdmaChObj       *appChObj        = &appObj->appChObj;
    App_UdmaTrObj       *appTrObj       = &appChObj->appTrObj;
    App_UdmaTestObj     *appTestObj     = &appObj->appTestObj;
    App_UdmaCounterObj  *appCounterObj  = &appObj->appCounterObj;
    Udma_DrvHandle       drvHandle      = &appObj->drvObj;

    //appTestObj->clk = 45000000U;

#if defined (SOC_AM64X)
    /* Use Block Copy DMA for AM64x */
    instId = UDMA_INST_ID_BCDMA_0;
#else
    /* Use MCU NAVSS for MCU domain cores. Rest all cores uses Main NAVSS */
#if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
    instId = UDMA_INST_ID_MCU_0;
#else
    instId = UDMA_INST_ID_MAIN_0;
#endif
#endif
    /* UDMA driver init */
    UdmaInitPrms_init(instId, &initPrms);
    initPrms.virtToPhyFxn   = &Udma_appVirtToPhyFxn;
    initPrms.phyToVirtFxn   = &Udma_appPhyToVirtFxn;
    initPrms.printFxn       = &App_print;
    retVal = Udma_init(drvHandle, &initPrms);
    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] UDMA init failed!!\n");
    }

    /* Init channel parameters */
    appChObj->chHandle          = &appChObj->chObj;
    appChObj->drvHandle         = drvHandle;
    appChObj->txRingMem         = &gTxRingMem[0U];
#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
    appChObj->tdCqEventHandle   = NULL;
    appChObj->txCompRingMem     = &gTxCompRingMem[0U];
    appChObj->txTdCompRingMem   = &gTxTdCompRingMem[0U];
#endif
    appChObj->trpdMem           = &gUdmaTrpdMem[0U];
    
    /* Init TR parameters */
    appTrObj->trEventHandle      = NULL;
    appTrObj->drvHandle          = drvHandle;

    memset((void *)&appCounterObj->txStartTicks,  0, sizeof(appCounterObj->txStartTicks));
    memset((void *)&appCounterObj->txStopTicks,   0, sizeof(appCounterObj->txStopTicks));
    memset((void *)&appCounterObj->txTotalTicks,  0, sizeof(appCounterObj->txTotalTicks));
    memset((void *)&appCounterObj->txElapsedTime, 0, sizeof(appCounterObj->txElapsedTime));
    memset((void *)&appCounterObj->rxStartTicks,  0, sizeof(appCounterObj->rxStartTicks));
    memset((void *)&appCounterObj->rxStopTicks,   0, sizeof(appCounterObj->rxStopTicks));
    memset((void *)&appCounterObj->rxTotalTicks,  0, sizeof(appCounterObj->rxTotalTicks));
    memset((void *)&appCounterObj->rxElapsedTime, 0, sizeof(appCounterObj->rxElapsedTime));

    if(UDMA_SOK == retVal)
    {
        retVal += App_ospiFlashInit(ospiObj, appTestObj->clk);
        
    }

    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] ospi Flash init failed!!\n");
    }

    return (retVal);
}


static int32_t App_deinit(App_UdmaObj *appObj, App_OspiObj *ospiObj)
{
    int32_t         retVal;
    Udma_DrvHandle  drvHandle = &appObj->drvObj;

    OspiFlash_ospiClose(ospiObj, FALSE);

    retVal = Udma_deinit(drvHandle);
    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] UDMA deinit failed!!\n");
    }

    return (retVal);
}
static int32_t App_create(App_UdmaObj *appObj)
{
    int32_t             retVal = UDMA_SOK;
    uint32_t            chType;
    Udma_ChPrms         chPrms;
    Udma_ChTxPrms       txPrms;
    Udma_ChRxPrms       rxPrms;
    Udma_EventHandle    eventHandle;
    App_UdmaChObj      *appChObj = &appObj->appChObj;
    App_UdmaTrObj      *appTrObj = &appChObj->appTrObj;
    Udma_ChHandle       chHandle = appChObj->chHandle;
    Udma_DrvHandle      drvHandle = &appObj->drvObj;

    if(UDMA_SOK == retVal)
    {
        /* Init channel parameters */
        chType = UDMA_CH_TYPE_TR_BLK_COPY;
        UdmaChPrms_init(&chPrms, chType);
        chPrms.fqRingPrms.ringMem       = appChObj->txRingMem;
        chPrms.fqRingPrms.ringMemSize   = UDMA_TEST_APP_RING_MEM_SIZE;
        chPrms.fqRingPrms.elemCnt       = UDMA_TEST_APP_RING_ENTRIES;
#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
        chPrms.cqRingPrms.ringMem       = appChObj->txCompRingMem;
        chPrms.cqRingPrms.ringMemSize   = UDMA_TEST_APP_RING_MEM_SIZE;
        chPrms.cqRingPrms.elemCnt       = UDMA_TEST_APP_RING_ENTRIES;
        chPrms.tdCqRingPrms.ringMem     = appChObj->txTdCompRingMem;
        chPrms.tdCqRingPrms.ringMemSize = UDMA_TEST_APP_RING_MEM_SIZE;
        chPrms.tdCqRingPrms.elemCnt     = UDMA_TEST_APP_RING_ENTRIES;
#endif

        /* Open channel for block copy */
        retVal = Udma_chOpen(drvHandle, chHandle, chType, &chPrms);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA channel open failed!!\n");
        }
    }

    if(UDMA_SOK == retVal)
    {
        /* Config TX channel */
        UdmaChTxPrms_init(&txPrms, chType);
        retVal = Udma_chConfigTx(chHandle, &txPrms);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA TX channel config failed!!\n");
        }
    }

    if(UDMA_SOK == retVal)
    {
        /* Config RX channel - which is implicitly paired to TX channel in
            * block copy mode */
        UdmaChRxPrms_init(&rxPrms, chType);
        retVal = Udma_chConfigRx(chHandle, &rxPrms);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA RX channel config failed!!\n");
        }
    }

    if(UDMA_SOK == retVal)
    {
        /* Register TR event */
        eventHandle = &appTrObj->trEventObj;
        UdmaEventPrms_init(&appTrObj->trEventPrms);
        appTrObj->trEventPrms.eventType         = UDMA_EVENT_TYPE_TR;
        appTrObj->trEventPrms.eventMode         = UDMA_EVENT_MODE_SHARED;
        appTrObj->trEventPrms.chHandle          = chHandle;
       /* For polling mode we can't use the existing master event as that is meant only for interrupt event - 
        *  we can't mix interrupt and poll mode in same master handle. Set the parameter to NULL 
        *  so that the driver creates a new master event. */
        appTrObj->trEventPrms.masterEventHandle = NULL;
        appTrObj->trEventPrms.eventCb           = NULL;
        appTrObj->trEventPrms.appData           = appChObj;
        retVal = Udma_eventRegister(drvHandle, eventHandle, &appTrObj->trEventPrms);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA TR event register failed!!\n");
        }
        else
        {
            appTrObj->trEventHandle = eventHandle;
        }
    }

#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
    if(UDMA_SOK == retVal)
    {
        /* Register teardown ring completion callback */
        eventHandle = &appChObj->tdCqEventObj;
        UdmaEventPrms_init(&appChObj->tdCqEventPrms);
        appChObj->tdCqEventPrms.eventType         = UDMA_EVENT_TYPE_TEARDOWN_PACKET;
        appChObj->tdCqEventPrms.eventMode         = UDMA_EVENT_MODE_SHARED;
        appChObj->tdCqEventPrms.chHandle          = chHandle;
        appChObj->tdCqEventPrms.masterEventHandle = Udma_eventGetGlobalHandle(drvHandle);
        appChObj->tdCqEventPrms.eventCb           = &App_udmaEventTdCb;
        appChObj->tdCqEventPrms.appData           = appChObj;
        retVal = Udma_eventRegister(drvHandle, eventHandle, &appChObj->tdCqEventPrms);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA Teardown CQ event register failed!!\n");
        }
        else
        {
            appChObj->tdCqEventHandle = eventHandle;
        }
    }
#endif 

    if(UDMA_SOK == retVal)
    {
        /* Channel enable */
        retVal = Udma_chEnable(chHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA channel enable failed!!\n");
        }
    }

    return (retVal);
}

static int32_t App_delete(App_UdmaObj *appObj)
{
    int32_t         retVal = UDMA_SOK, tempRetVal;
    uint64_t        pDesc;
    App_UdmaChObj  *appChObj = &appObj->appChObj;
    App_UdmaTrObj  *appTrObj = &appChObj->appTrObj;
    Udma_ChHandle   chHandle = appChObj->chHandle;
    

    /* Flush any pending request from the free queue */
    while(1)
    {
        tempRetVal = Udma_ringFlushRaw(
                            Udma_chGetFqRingHandle(chHandle), &pDesc);
        if(UDMA_ETIMEOUT == tempRetVal)
        {
            break;
        }
    }

    /* Unregister all events */
    if(NULL != appTrObj->trEventHandle)
    {
        retVal = Udma_eventUnRegister(appTrObj->trEventHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("\n [Error] UDMA event unregister failed!!\n");
        }
        appTrObj->trEventHandle = NULL;
    }
#if (UDMA_SOC_CFG_RA_NORMAL_PRESENT == 1)
    if(NULL != appChObj->tdCqEventHandle)
    {
        retVal += Udma_eventUnRegister(appChObj->tdCqEventHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA event unregister failed!!\n");
        }
        appChObj->tdCqEventHandle = NULL;
    }
#endif

    retVal += Udma_chClose(chHandle);
    if(UDMA_SOK != retVal)
    {
        App_print("\n [Error] UDMA channel close failed!!\n");
    }

    return (retVal);
}

static void App_udmaTrpdInit(App_UdmaTrObj *appTrObj, App_UdmaChObj  *appChObj)
{    
    CSL_UdmapCppi5TRPD *pTrpd = (CSL_UdmapCppi5TRPD *) appChObj->trpdMem;
    CSL_UdmapTR15 *pTr = (CSL_UdmapTR15 *)(appChObj->trpdMem + sizeof(CSL_UdmapTR15));
    uint32_t *pTrResp = (uint32_t *) (appChObj->trpdMem + (sizeof(CSL_UdmapTR15) * 2U));
    uint32_t cqRingNum = Udma_chGetCqRingNum(appChObj->chHandle);

    /* Make TRPD */
    UdmaUtils_makeTrpd(pTrpd, UDMA_TR_TYPE_15, 1U, cqRingNum);
    CSL_udmapCppi5TrSetReload((CSL_UdmapCppi5TRPD*)pTrpd, appTrObj->reloadCnt, 0U);

    /* Setup TR */
    pTr->flags  = CSL_FMK(UDMAP_TR_FLAGS_TYPE, CSL_UDMAP_TR_FLAGS_TYPE_4D_BLOCK_MOVE_REPACKING_INDIRECTION);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOL, appTrObj->eolType);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE, appTrObj->eventSize);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, appTrObj->trigger);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE, appTrObj->triggerType);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOP, 1U);
    
    pTr->icnt0    = appTrObj->icnt[0];
    pTr->icnt1    = appTrObj->icnt[1];
    pTr->icnt2    = appTrObj->icnt[2];
    pTr->icnt3    = appTrObj->icnt[3];
    pTr->addr     = (uint64_t) Udma_appVirtToPhyFxn(appTrObj->addr, 0U, NULL);
    pTr->fmtflags = 0x00000000U;        /* Linear addressing, 1 byte per elem.
                                           Replace with CSL-FL API */

    pTr->dicnt0   = appTrObj->dicnt[0];
    pTr->dicnt1   = appTrObj->dicnt[1];
    pTr->dicnt2   = appTrObj->dicnt[2];
    pTr->dicnt3   = appTrObj->dicnt[3];
    pTr->daddr    = (uint64_t) Udma_appVirtToPhyFxn(appTrObj->daddr, 0U, NULL);

    pTr->dim1     = appTrObj->dim[0]; 
    pTr->dim2     = appTrObj->dim[1]; 
    pTr->dim3     = appTrObj->dim[2]; 
    pTr->ddim1    = appTrObj->ddim[0]; 
    pTr->ddim2    = appTrObj->ddim[1]; 
    pTr->ddim3    = appTrObj->ddim[2];

    /* Clear TR response memory */
    *pTrResp = 0xFFFFFFFFU;

    /* Writeback cache */
    Udma_appUtilsCacheWb(appChObj->trpdMem, UDMA_TEST_APP_TRPD_SIZE_ALIGN);

    return;
}

#if defined(FLASH_TYPE_OSPI)
static int32_t App_udmaTrpdSanityCheck(App_UdmaChObj *appChObj, uint64_t pDesc)
{
    int32_t         retVal  = UDMA_SOK;
    uint32_t       *pTrResp, trRespStatus;
    uint8_t        *trpdMem = appChObj->trpdMem;

    /* Check returned descriptor pointer */
    if(((uint64_t) Udma_appPhyToVirtFxn(pDesc, 0U, NULL)) != ((uint64_t) trpdMem))
    {
        App_print("\n [Error] TR descriptor pointer returned doesn't "
                "match the submitted address!!\n");
        retVal = UDMA_EFAIL;
    }

    if(UDMA_SOK == retVal)
    {
        /* Invalidate cache */
        Udma_appUtilsCacheInv(trpdMem, UDMA_TEST_APP_TRPD_SIZE_ALIGN);

        /* check TR response status */
        pTrResp = (uint32_t *) (trpdMem + (sizeof(CSL_UdmapTR15) * 2U));
        trRespStatus = CSL_FEXT(*pTrResp, UDMAP_TR_RESPONSE_STATUS_TYPE);
        if(trRespStatus != CSL_UDMAP_TR_RESPONSE_STATUS_COMPLETE)
        {
            App_print("\n [Error] TR Response not completed!!\n");
            retVal = UDMA_EFAIL;
        }
    }
    
    return (retVal);
}
#endif

static inline void App_udmaTrObjInitRead(App_UdmaTestObj *appTestObj, App_UdmaTrObj *appTrObj)
{
    /* TR Reload Count */
    appTrObj->reloadCnt    = 0x1FFU; /* Set to 0x1FFU for perpetual loop */
    appTrObj->trigger      = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0;
    /* Set interrupt after transferring icnt0*icnt1*icnt2*icnt3 bytes - When TR is completed */
    appTrObj->eventSize    = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION; 
    /* Transfer icnt0*icnt1*icnt2*icnt3 bytes(entire TR) after a trigger */
    appTrObj->triggerType  = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL;
    /* EOL boundaries for each icnt0*icnt1*icnt2*icnt3 bytes */
    appTrObj->eolType      = CSL_UDMAP_TR_FLAGS_EOL_ICNT0_ICNT1_ICNT2_ICNT3; 

    /* No. of bytes to tansfer after getting interrupt (in this case)*/
    appTrObj->icnt[0] = appTestObj->numBytes; 
    /* No. of times to repeat the tansfer of inct0 bytes */
    appTrObj->icnt[1] = 1U;
    /* No. of times to repeat the tansfer of inct0*icnt1 bytes */
    appTrObj->icnt[2] = 1U;
    /* No. of times to repeat the tansfer of inct0*icnt1*inct2 bytes */
    appTrObj->icnt[3] = 1U;
    /* similar destination params */
    appTrObj->dicnt[0] = appTestObj->numBytes; 
    appTrObj->dicnt[1] = 1U;
    appTrObj->dicnt[2] = 1U;
    appTrObj->dicnt[3] = 1U;

    /* DIM1: Offset for source OSPI data address after transferring inct0 bytes */
    appTrObj->dim[0]  = appTrObj->icnt[0]; /* Use inct0 bytes so that successive triger tranfers the next icnt0 bytes */
    /* DIM2 - Offset for source OSPI data address after transferring inct0*inct1 bytes */
    appTrObj->dim[1]  = appTrObj->icnt[0]*appTrObj->icnt[1]; /* Use inct0*icnt1 bytes so that successive iteration tranfers the next icnt0*icnt1 bytes */
    /* DIM3 - Offset for source OSPI data address after transferring inct0*inct1*inct2 bytes */
    appTrObj->dim[2]  = appTrObj->icnt[0]*appTrObj->icnt[1]*appTrObj->icnt[2]; /* Use inct0*icnt1*icnt2 bytes so that successive iteration tranfers the next inct0*icnt1*icnt2 bytes */

    /* Similar offset for destination RX buffer address */
    appTrObj->ddim[0]  = appTrObj->dicnt[0]; 
    appTrObj->ddim[1]  = appTrObj->dicnt[0]*appTrObj->dicnt[1];
    appTrObj->ddim[2]  = appTrObj->dicnt[0]*appTrObj->dicnt[1]*appTrObj->dicnt[2];

    /* Source Address - OSPI Data address */
    appTrObj->addr  = gUdmaTestOspiFlashDataAddr;
    /* Destination Address - RX Buffer */
    appTrObj->daddr  = &gUdmaTestRxBuf[0U];;

    return;
}

#if defined(FLASH_TYPE_OSPI)
static inline void App_udmaTrObjInitWrite(App_UdmaTestObj *appTestObj, App_UdmaTrObj *appTrObj)
{
    /* TR Reload Count */
    appTrObj->reloadCnt    = 0U; 
    appTrObj->trigger      = CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0;
    /* Set interrupt after transferring icnt0 bytes */
    appTrObj->eventSize    = CSL_UDMAP_TR_FLAGS_EVENT_SIZE_ICNT1_DEC; 
    /* Transfer icnt0 bytes after a trigger */
    appTrObj->triggerType  = CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT1_DEC;
    /* EOL boundaries for each icnt0 bytes */
    appTrObj->eolType      = CSL_UDMAP_TR_FLAGS_EOL_ICNT0; 

    if(appTestObj->numBytes > UDMA_TEST_WRITE_CHUNK_SIZE)
    {
        /* For OSPI DMA write, write in chunks. No. of bytes to tansfer after getting interrupt(in this case) */
        appTrObj->icnt[0] = UDMA_TEST_WRITE_CHUNK_SIZE; 
        /* No. of times to repeat the tansfer of inct0 bytes (= No.of chunks in this case) */
        appTrObj->icnt[1] = appTestObj->numBytes/UDMA_TEST_WRITE_CHUNK_SIZE;

        appTrObj->dicnt[0] = UDMA_TEST_WRITE_CHUNK_SIZE; 
        appTrObj->dicnt[1] = appTestObj->numBytes/UDMA_TEST_WRITE_CHUNK_SIZE;
    }
    else
    {
        appTrObj->icnt[0] = appTestObj->numBytes;
        appTrObj->icnt[1] = 1U;
        
        appTrObj->dicnt[0] = appTestObj->numBytes;
        appTrObj->dicnt[1] = 1U;
    }
    
    appTrObj->icnt[2] = 1U;
    appTrObj->icnt[3] = 1U;
    
    appTrObj->dicnt[2] = 1U;
    appTrObj->dicnt[3] = 1U;

    /* DIM1- Offset for source TX Buffer address after transferring inct0 bytes */
    appTrObj->dim[0]  = appTrObj->icnt[0]; /* chunkSize - so that successive triger tranfers the next icnt0(chunkSize) bytes */
    /* DIM2 - Offset for source TX Buffer address after transferring inct0*inct1 bytes */
    appTrObj->dim[1]  = appTrObj->icnt[0]*appTrObj->icnt[1]; /* inct0*icnt1 bytes - so that successive iteration tranfers the next icnt0*icnt1 bytes */
    /* DIM3 - Offset for source TX Buffer address after transferring inct0*inct1*inct2 bytes */
    appTrObj->dim[2]  = appTrObj->icnt[0]*appTrObj->icnt[1]*appTrObj->icnt[2]; /* inct0*icnt1*icnt2 bytes - so that successive iteration tranfers the next inct0*icnt1*icnt2 bytes */

    /* DDIM1/DDIM2/DDIM3 - Similar offset for destination RX buffer address */
    appTrObj->ddim[0]  = appTrObj->dicnt[0]; 
    appTrObj->ddim[1]  = appTrObj->dicnt[0]*appTrObj->dicnt[1];
    appTrObj->ddim[2]  = appTrObj->dicnt[0]*appTrObj->dicnt[1]*appTrObj->dicnt[2];

    /* Source Address - TX Buffer */
    appTrObj->addr  = &gUdmaTestTxBuf[0U];
    /* Destination Address - OSPI Data address  */
    appTrObj->daddr = gUdmaTestOspiFlashDataAddr;

    return;
}
#endif

static void App_printPerfResults(App_UdmaObj *appObj)
{    
    App_UdmaCounterObj  *appCounterObj = &appObj->appCounterObj;
    App_UdmaTestObj     *appTestObj = &appObj->appTestObj;
    uint32_t             tCnt;
    uint32_t             triggerCnt;
    
    appCounterObj->txTotalTicks = appCounterObj->txStopTicks - appCounterObj->txStartTicks;
    appCounterObj->txElapsedTime = (appCounterObj->txTotalTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;

    App_printNum("\n OSPI Write %d", appTestObj->numBytes);
    App_printNum(" bytes in %d", (uint32_t)appCounterObj->txElapsedTime);
    App_print("ns.");

    if(appTestObj->testId != UDMA_OSPI_FLASH_TEST_ID_WR_TUNING)
    {
        triggerCnt = UDMA_TEST_XFER_REPEAT_CNT;
        for(tCnt = 0U; tCnt < triggerCnt; tCnt++)
        {
            appCounterObj->rxTotalTicks[tCnt] = appCounterObj->rxStopTicks[tCnt] - appCounterObj->rxStartTicks[tCnt];
            appCounterObj->rxTotalTicks[triggerCnt] += appCounterObj->rxTotalTicks[tCnt];
            appCounterObj->rxElapsedTime[tCnt] = (appCounterObj->rxTotalTicks[tCnt]*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;

            App_printNum("\n OSPI Read %d", appTestObj->numBytes);
            App_printNum(" bytes in %d", (uint32_t)appCounterObj->rxElapsedTime[tCnt]);
            App_print("ns.");
        }
        
        appCounterObj->rxTotalTicks[triggerCnt] = appCounterObj->rxTotalTicks[triggerCnt]/triggerCnt;
        appCounterObj->rxElapsedTime[triggerCnt] = (appCounterObj->rxTotalTicks[triggerCnt]*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;
        App_printNum("\n\n Average time for OSPI Read %d", appTestObj->numBytes);
        App_printNum(" bytes = %d", (uint32_t)appCounterObj->rxElapsedTime[triggerCnt]);
        App_print("ns. \n\n");
    }

    return;
}

void App_print(const char *str)
{
    UART_printf("%s", str);
    if(TRUE == Udma_appIsPrintSupported())
    {
        printf("%s", str);
    }

    return;
}

static void App_printNum(const char *str, uint32_t num)
{
    static char printBuf[200U];

    snprintf(printBuf, 200U, str, num);
    UART_printf("%s", printBuf);

    if(TRUE == Udma_appIsPrintSupported())
    {
        printf("%s", printBuf);
    }

    return;
}

int32_t App_setGTCClk(uint32_t moduleId,
                      uint32_t clkId,
                      uint64_t clkRateHz)
{
    int32_t retVal;
    uint64_t currClkFreqHz;

    retVal = Sciclient_pmGetModuleClkFreq(moduleId,
                                          clkId,
                                          &currClkFreqHz,
                                          SCICLIENT_SERVICE_WAIT_FOREVER);
    if ((retVal == CSL_PASS) &&
        (currClkFreqHz != clkRateHz))
    {
        retVal = OspiFlash_ClkRateSet(moduleId, clkId, clkRateHz);
    }

    /* Enable GTC */
    HW_WR_REG32(CSL_GTC0_GTC_CFG1_BASE + 0x0U, 0x1);

    return (retVal);
}

static int32_t App_ospiFlashInit(App_OspiObj *ospiObj, uint32_t clk)
{
    int32_t status = UDMA_SOK;
    bool dacMode;

#if defined(FLASH_TYPE_OSPI)
    dacMode = TRUE;
#else
    dacMode = FALSE;
#endif

    OspiFlash_spiPhyTuneReset(TRUE);

    status += OspiFlash_ospiConfigClk(clk);
    if(UDMA_SOK == status)
    {
        App_printNum("\n OSPI RCLK running at %d Hz. \n", clk);
    }

    ospiObj->clk = clk;
    status += OspiFlash_ospiOpen(ospiObj, OSPI_FLASH_WRITE_TIMEOUT, OSPI_FLASH_CHECK_IDLE_DELAY, dacMode, FALSE);
    if(UDMA_SOK != status)
    {
        App_print("\n [Error] ospi open failed. \n");
    }

    status += OspiFlash_ospiEnableDDR(dacMode, FALSE);
    if(UDMA_SOK != status)
    {
        App_print("\n [Error] ospi Disable DDR failed. \n");
    }

    status += OspiFlash_ospiSetOpcode(dacMode);
        if(UDMA_SOK != status)
    {
        App_print("\n [Error] ospi set dac Mode failed. \n");
    }

#if defined(FLASH_TYPE_OSPI)
    status += OspiFlash_ospiConfigPHY(clk, FALSE);
#endif

    if(UDMA_SOK != status)
    {
        App_print("\n [Error] ospi disable PHY failed. \n");
    }
    return (status);    
}

void App_ospiFlashConfigDacMode( App_OspiObj *ospiObj, bool dacMode)
{
    OspiFlash_ospiClose(ospiObj, FALSE);
    OspiFlash_ospiOpen(ospiObj, OSPI_FLASH_WRITE_TIMEOUT, OSPI_FLASH_CHECK_IDLE_DELAY, TRUE, TRUE);
    OspiFlash_ospiEnableDDR(dacMode, FALSE);
    OspiFlash_ospiSetOpcode(dacMode);
}

#if defined(FLASH_TYPE_OSPI)
static int32_t App_ospiFlashStart(uint32_t numBytes)
{
    int32_t retVal = UDMA_SOK;
    const CSL_ospi_flash_cfgRegs *baseAddr = (const CSL_ospi_flash_cfgRegs *)(OSPI_FLASH_CONFIG_REG_BASE_ADDR);

    retVal = OspiFlash_ospiEraseBlk(0U, numBytes, FALSE);

    OspiFlash_ospiXferIntrInit(FALSE);

    /* Enable PHY pipeline mode */
    CSL_ospiPipelinePhyEnable(baseAddr, TRUE);

    return (retVal);
}
#endif

0 Parth Nagpal over 1 year ago in reply to Daviel Almonte

TI__Mastermind 42135 points

Hi Daviel,

I would recommend you to use OSPI driver example instead. The UDMA example uses the CSL layer (which might be outdated) and not the driver.

Regards,
Parth

0 Daviel Almonte over 1 year ago in reply to Parth Nagpal

TI__Expert 3285 points

Hey Parth,

We ran the csl_ospi_flash_app demo. it fails at Phy tuning again.

1. is there a way to run indac to skip the phy tuning?

2. is it possible to to run the ospi clk at 45MHz? ZF performed the Signal integrity analysis only to 45MHz. Beyond 45MHZ, they don’t have the confidence that OSPI will meet the timing requirements due to stubs in our design.

Src code: csl_ospi_flash_app

/**
 *  \file   ospi_flash_app_main.c
 *
 *  \brief  OSPI Flash test application main file.
 *
 */
 /*
 *  Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
 /**
 *  \file   main.c
 *
 *  \brief This file contains the OSPI Flash application which demonstrates
 *         ospi flash read and write.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include "ospi_flash_app_test.h"

#ifdef UNITY_INCLUDE_CONFIG_H
#include <ti/build/unit-test/Unity/src/unity.h>
#include <ti/build/unit-test/config/unity_config.h>
#endif

/* Unity test functions */
void test_csl_ospi_flash_app_runner(void);
void test_csl_ospi_flash_app(void);

/* ========================================================================== */
/*                                 Macros                                     */
/* ========================================================================== */

#define OSPI_FLASH_TEST_MAX_BUF_LEN       (1024U) 
#define PRINT_WRITE_PERF
#define PRINT_READ_PERF

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

uint8_t txBuf[OSPI_FLASH_TEST_MAX_BUF_LEN]  __attribute__((aligned(128))) __attribute__((section(".ospi_buffer_r5_tcm")));
uint8_t rxBuf[OSPI_FLASH_TEST_MAX_BUF_LEN]  __attribute__((aligned(128))) __attribute__((section(".ospi_buffer_r5_tcm")));

volatile uint64_t   getTicksDelay = 0;          /* No.of ticks taken to do a GTC Reg Read operation */
volatile uint64_t   configStartTicks_T0;        /* GTC Timer ticks at start of configuration */
volatile uint64_t   configStopTicks_T1;         /* GTC Timer ticks at stop of configuration */
volatile uint64_t   transactionStartTicks_T2;   /* GTC Timer ticks at start of transaction */
volatile uint64_t   transcationStopTicks_T5;    /* GTC Timer ticks at stop of transaction */
volatile uint64_t   configTicks;                /* measured total no. of GTC Timer ticks for configuration*/
volatile uint64_t   transactionTicks;           /* measured total no. of GTC Timer ticks for transaction*/
volatile uint64_t   configTime;                 /* configuration time in nsec */
volatile uint64_t   transactionTime;            /* transaction time in nsec */

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

static void Ospi_flashTest(App_OspiObj *ospiObj);
static int32_t Ospi_flashSetGTCClk(uint32_t moduleId,
                                   uint32_t clkId,
                                   uint64_t clkRateHz);

static int32_t Ospi_flashTestRun(App_OspiObj *ospiObj, void *test);
static int32_t OspiFlashTest_init(App_OspiObj *ospiObj, void *test);
static int32_t OspiFlashTest_transfer(App_OspiObj *ospiObj, void *test);
static void OspiFlashTest_deinit(App_OspiObj *ospiObj, void *test);
static void OspiFlash_generatePattern(uint8_t *txBuf, 
                                      uint8_t *rxBuf, 
                                      uint32_t length);

static int32_t OspiFlash_DAC_write(uint8_t *buf, uint32_t numBytes)  __attribute__((section(".ospi_critical_fxns")));
static int32_t OspiFlash_DAC_read(uint8_t *buf, uint32_t numBytes) __attribute__((section(".ospi_critical_fxns")));

static int32_t OspiFlash_verifyData(uint8_t *expData,
                                    uint8_t *rxData,
                                    uint32_t length);

static int32_t OspiFlash_INDAC_write(App_OspiObj *ospiObj, uint8_t *buf, uint32_t numBytes, bool intrPollMode) __attribute__((section(".ospi_critical_fxns")));
static int32_t OspiFlash_INDAC_read(App_OspiObj *ospiObj, uint8_t *buf, uint32_t numBytes, bool intrPollMode) __attribute__((section(".ospi_critical_fxns")));


/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

App_OspiObj gOspiAppObj;

/* OSPI Flash Tests data structure */
OSPI_Flash_Tests Ospi_Flash_tests[] =
{
    /* testFunc,        testID,                                     clk,                    dacMode,        intrPollMode,   numBytes,   testDesc */
#if !defined(FLASH_TYPE_XSPI)
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_133M_16B,            OSPI_MODULE_CLK_133M,   TRUE,           TRUE,           16U,        "\r\n OSPI flash test DAC at 133MHz RCLK - Read/Write 16 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_166M_16B,            OSPI_MODULE_CLK_166M,   TRUE,           TRUE,           16U,        "\r\n OSPI flash test DAC at 166MHz RCLK - Read/Write 16 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_133M_32B,            OSPI_MODULE_CLK_133M,   TRUE,           TRUE,           32U,        "\r\n OSPI flash test DAC at 133MHz RCLK - Read/Write 32 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_166M_32B,            OSPI_MODULE_CLK_166M,   TRUE,           TRUE,           32U,        "\r\n OSPI flash test DAC at 166MHz RCLK - Read/Write 32 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_133M_64B,            OSPI_MODULE_CLK_133M,   TRUE,           TRUE,           64U,        "\r\n OSPI flash test DAC at 133MHz RCLK - Read/Write 64 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_166M_64B,            OSPI_MODULE_CLK_166M,   TRUE,           TRUE,           64U,        "\r\n OSPI flash test DAC at 166MHz RCLK - Read/Write 64 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_133M_128B,           OSPI_MODULE_CLK_133M,   TRUE,           TRUE,           128U,       "\r\n OSPI flash test DAC at 133MHz RCLK - Read/Write 128 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_166M_128B,           OSPI_MODULE_CLK_166M,   TRUE,           TRUE,           128U,       "\r\n OSPI flash test DAC at 166MHz RCLK - Read/Write 128 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_133M_256B,           OSPI_MODULE_CLK_133M,   TRUE,           TRUE,           256U,       "\r\n OSPI flash test DAC at 133MHz RCLK - Read/Write 256 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_166M_256B,           OSPI_MODULE_CLK_166M,   TRUE,           TRUE,           256U,       "\r\n OSPI flash test DAC at 166MHz RCLK - Read/Write 256 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_133M_512B,           OSPI_MODULE_CLK_133M,   TRUE,           TRUE,           512U,       "\r\n OSPI flash test DAC at 133MHz RCLK - Read/Write 512 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_166M_512B,           OSPI_MODULE_CLK_166M,   TRUE,           TRUE,           512U,       "\r\n OSPI flash test DAC at 166MHz RCLK - Read/Write 512 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_133M_1024B,          OSPI_MODULE_CLK_133M,   TRUE,           TRUE,           1024U,      "\r\n OSPI flash test DAC at 133MHz RCLK - Read/Write 1024 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_DAC_166M_1024B,          OSPI_MODULE_CLK_166M,   TRUE,           TRUE,           1024U,      "\r\n OSPI flash test DAC at 166MHz RCLK - Read/Write 1024 Bytes"},
#else
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_133M_16B,     OSPI_MODULE_CLK_133M,   FALSE,          TRUE,           16U,        "\r\n OSPI flash test INDAC POLL at 133MHz RCLK - Read/Write 16 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_166M_16B,     OSPI_MODULE_CLK_166M,   FALSE,          TRUE,           16U,        "\r\n OSPI flash test INDAC POLL at 166MHz RCLK - Read/Write 16 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_133M_32B,     OSPI_MODULE_CLK_133M,   FALSE,          TRUE,           32U,        "\r\n OSPI flash test INDAC POLL at 133MHz RCLK - Read/Write 32 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_166M_32B,     OSPI_MODULE_CLK_166M,   FALSE,          TRUE,           32U,        "\r\n OSPI flash test INDAC POLL at 166MHz RCLK - Read/Write 32 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_133M_64B,     OSPI_MODULE_CLK_133M,   FALSE,          TRUE,           64U,        "\r\n OSPI flash test INDAC POLL at 133MHz RCLK - Read/Write 64 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_166M_64B,     OSPI_MODULE_CLK_166M,   FALSE,          TRUE,           64U,        "\r\n OSPI flash test INDAC POLL at 166MHz RCLK - Read/Write 64 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_133M_128B,    OSPI_MODULE_CLK_133M,   FALSE,          TRUE,           128U,       "\r\n OSPI flash test INDAC POLL at 133MHz RCLK - Read/Write 128 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_166M_128B,    OSPI_MODULE_CLK_166M,   FALSE,          TRUE,           128U,       "\r\n OSPI flash test INDAC POLL at 166MHz RCLK - Read/Write 128 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_133M_256B,    OSPI_MODULE_CLK_133M,   FALSE,          TRUE,           256U,       "\r\n OSPI flash test INDAC POLL at 133MHz RCLK - Read/Write 256 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_POLL_166M_256B,    OSPI_MODULE_CLK_166M,   FALSE,          TRUE,           256U,       "\r\n OSPI flash test INDAC POLL at 166MHz RCLK - Read/Write 256 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_133M_16B,     OSPI_MODULE_CLK_133M,   FALSE,          FALSE,          16U,        "\r\n OSPI flash test INDAC INTR at 133MHz RCLK - Read/Write 16 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_166M_16B,     OSPI_MODULE_CLK_166M,   FALSE,          FALSE,          16U,        "\r\n OSPI flash test INDAC INTR at 166MHz RCLK - Read/Write 16 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_133M_32B,     OSPI_MODULE_CLK_133M,   FALSE,          FALSE,          32U,        "\r\n OSPI flash test INDAC INTR at 133MHz RCLK - Read/Write 32 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_166M_32B,     OSPI_MODULE_CLK_166M,   FALSE,          FALSE,          32U,        "\r\n OSPI flash test INDAC INTR at 166MHz RCLK - Read/Write 32 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_133M_64B,     OSPI_MODULE_CLK_133M,   FALSE,          FALSE,          64U,        "\r\n OSPI flash test INDAC INTR at 133MHz RCLK - Read/Write 64 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_166M_64B,     OSPI_MODULE_CLK_166M,   FALSE,          FALSE,          64U,        "\r\n OSPI flash test INDAC INTR at 166MHz RCLK - Read/Write 64 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_133M_128B,    OSPI_MODULE_CLK_133M,   FALSE,          FALSE,          128U,       "\r\n OSPI flash test INDAC INTR at 133MHz RCLK - Read/Write 128 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_166M_128B,    OSPI_MODULE_CLK_166M,   FALSE,          FALSE,          128U,       "\r\n OSPI flash test INDAC INTR at 166MHz RCLK - Read/Write 128 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_133M_256B,    OSPI_MODULE_CLK_133M,   FALSE,          FALSE,          256U,       "\r\n OSPI flash test INDAC INTR at 133MHz RCLK - Read/Write 256 Bytes"},
    {Ospi_flashTestRun, OSPI_FLASH_TEST_ID_INDAC_INTR_166M_256B,    OSPI_MODULE_CLK_166M,   FALSE,          FALSE,          256U,       "\r\n OSPI flash test INDAC INTR at 166MHz RCLK - Read/Write 256 Bytes"},
#endif    
    {NULL, }
};

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
void test_csl_ospi_flash_app(void)
{

    Board_initCfg boardCfg;
    Board_STATUS  boardStatus;
    int32_t       status;
    App_OspiObj   *ospiObj = &gOspiAppObj;

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
               BOARD_INIT_MODULE_CLOCK |
               BOARD_INIT_UART_STDIO;
               
    boardStatus = Board_init(boardCfg);

#if defined (UNITY_INCLUDE_CONFIG_H)
    TEST_ASSERT_EQUAL_INT32(BOARD_SOK, boardStatus);
#endif

    if (boardStatus != BOARD_SOK)
    {
        OSPI_FLASH_log("[Error] Board init failed!!\n");
    }

    /* Configure GTC Timer for profiling */
    status = Ospi_flashSetGTCClk(OSPI_FLASH_GTC_MOD_ID,
                                 OSPI_FLASH_GTC_CLK_ID,
                                 OSPI_FLASH_GTC_CLK_FREQ);
#if defined (UNITY_INCLUDE_CONFIG_H)
    TEST_ASSERT_EQUAL_INT32(CSL_PASS, status);
#endif

    if (CSL_PASS != status)
    {
        OSPI_FLASH_log("[Error] Configure GTC Timer failed!!\n");
    }

    Ospi_flashTest(ospiObj);

    return;
}

static int32_t Ospi_flashSetGTCClk(uint32_t moduleId,
                                   uint32_t clkId,
                                   uint64_t clkRateHz)
{
    int32_t status = OSPI_FLASH_APP_STATUS_SUCCESS;
    uint64_t currClkFreqHz;

    status = Sciclient_pmGetModuleClkFreq(moduleId,
                                          clkId,
                                          &currClkFreqHz,
                                          SCICLIENT_SERVICE_WAIT_FOREVER);
    if ((status == CSL_PASS) &&
        (currClkFreqHz != clkRateHz))
    {
        status = OspiFlash_ClkRateSet(moduleId, clkId, clkRateHz);
    }

    /* Enable GTC */
    HW_WR_REG32(CSL_GTC0_GTC_CFG1_BASE + 0x0U, 0x1);

    /* Measure and store the time spent to do a getTime operation */
    getTicksDelay = OspiFash_getGTCTimerTicks();
    getTicksDelay = OspiFash_getGTCTimerTicks() - getTicksDelay;
    OSPI_FLASH_log("\n Time taken to read GTC Timer ticks = %d ns (%d ticks) ",
                   (uint32_t)((getTicksDelay*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ), 
                   (uint32_t)getTicksDelay);

    return (status);
}

static void Ospi_flashTest(App_OspiObj *ospiObj)
{
    uint32_t    i;
    Bool        testFail = FALSE;
    int32_t     status = OSPI_FLASH_APP_STATUS_SUCCESS;
    OSPI_Flash_Tests *test;

    for (i = 0;  ; i++)                 
    {
        test = &Ospi_Flash_tests[i];
        if (test->testFunc == NULL)
        {
            break;
        }

        status = test->testFunc((App_OspiObj *)ospiObj, (void *)test);

#if defined (UNITY_INCLUDE_CONFIG_H)
        TEST_ASSERT_EQUAL_INT32(OSPI_FLASH_APP_STATUS_SUCCESS, status);
#endif
        if(OSPI_FLASH_APP_STATUS_SUCCESS == status)
        {
            OSPI_FLASH_log("\r\n %s have passed\r\n", test->testDesc);
        }
        else
        {
            OSPI_FLASH_log("\r\n %s have failed\r\n", test->testDesc);
            testFail = TRUE;
            break;
        }
    }

#if defined (UNITY_INCLUDE_CONFIG_H)
    TEST_ASSERT_EQUAL_UINT32(FALSE, testFail);
#endif
    if(TRUE == testFail)
    {
        OSPI_FLASH_log("\n Some tests have failed. \n");
    }
    else
    {
        OSPI_FLASH_log("\n All tests have passed. \n");
    }

    OSPI_FLASH_log("Done\n");

    while (true)
    {
    }
}

static int32_t Ospi_flashTestRun(App_OspiObj *ospiObj, void *test)
{
    int32_t status = OSPI_FLASH_APP_STATUS_SUCCESS;

    configStartTicks_T0 = OspiFash_getGTCTimerTicks();
    status = OspiFlashTest_init(ospiObj, test);
    
    if(OSPI_FLASH_APP_STATUS_SUCCESS != status)
    {
        OSPI_FLASH_log("[Error] OSPI Flash Test init failed!!\n");
    }
    else
    {
        status = OspiFlashTest_transfer(ospiObj, test);
        if(OSPI_FLASH_APP_STATUS_SUCCESS != status)
        {
            OSPI_FLASH_log("[Error] OSPI Flash Test transfer failed!!\n");
        }

        OspiFlashTest_deinit(ospiObj, test);
    }

    return (status);
}

/*
** This function will call the necessary CSL ospi APIs which will configure the
** OSPI controller.
*/
static int32_t OspiFlashTest_init(App_OspiObj *ospiObj, void *test)
{
    int32_t status = OSPI_FLASH_APP_STATUS_SUCCESS;

    OSPI_Flash_Tests    *pTest = (OSPI_Flash_Tests *)test;

    status += OspiFlash_ospiConfigClk(pTest->clk);
    if(OSPI_FLASH_APP_STATUS_SUCCESS == status)
    {
        OSPI_FLASH_log("\n OSPI RCLK running at %d Hz. \n", pTest->clk);
    }

    /* Print test description */
    OSPI_FLASH_log("\r\n %s\r\n", pTest->testDesc);

    status += OspiFlash_ospiOpen(ospiObj, OSPI_FLASH_WRITE_TIMEOUT, OSPI_FLASH_CHECK_IDLE_DELAY, pTest->dacMode, pTest->intrPollMode);

    if(OSPI_FLASH_APP_STATUS_SUCCESS != status)
    {
        OSPI_FLASH_log("[Error] OSPI open failed!!\n");
    }

    /* TO DO : If supporting Legacy SPI mode, the following should be based on dtrEnable.
    * ie, if Legacy SPI mode -> dtrEnable will be false -> Enable SDR instead */
    status += OspiFlash_ospiEnableDDR(pTest->dacMode, pTest->intrPollMode);
    if(OSPI_FLASH_APP_STATUS_SUCCESS != status)
    {
        OSPI_FLASH_log("[Error] OSPI Enable DDR failed!!\n");
    }

    status += OspiFlash_ospiSetOpcode(pTest->dacMode);
    if(OSPI_FLASH_APP_STATUS_SUCCESS != status)
    {
        OSPI_FLASH_log("[Error] OSPI set Opcode failed!!\n");
    }

    /* If non DAC /Legacy SPI mode, no need to config PHY, skip this */
    if(pTest->dacMode)    
    {
        status += OspiFlash_ospiConfigPHY(pTest->clk, pTest->intrPollMode);
        if(OSPI_FLASH_APP_STATUS_SUCCESS != status)
            {
                OSPI_FLASH_log("[Error] OSPI enable Phy failed!!\n");
            }
    }

    return (status);    
}

static int32_t OspiFlashTest_transfer(App_OspiObj *ospiObj, void *test)
{
    int32_t status = OSPI_FLASH_APP_STATUS_SUCCESS;
    OSPI_Flash_Tests    *pTest = (OSPI_Flash_Tests *)test;

    OspiFlash_generatePattern(txBuf, rxBuf, pTest->numBytes);

    status += OspiFlash_ospiEraseBlk(0U, pTest->numBytes, pTest->intrPollMode);

    if(pTest->dacMode) 
    {
        status += OspiFlash_DAC_write(txBuf, pTest->numBytes);
        status += OspiFlash_DAC_read(rxBuf, pTest->numBytes);
    }
    else                    
    {
        status += OspiFlash_INDAC_write(ospiObj, txBuf, pTest->numBytes, pTest->intrPollMode);
        status += OspiFlash_INDAC_read(ospiObj, rxBuf, pTest->numBytes, pTest->intrPollMode);
    }
    

    /* Verify whether the data written and read are Equal */
    status += OspiFlash_verifyData(txBuf, rxBuf, pTest->numBytes);

    return (status);    
}

static void OspiFlashTest_deinit(App_OspiObj *ospiObj, void *test)
{
    OSPI_Flash_Tests    *pTest = (OSPI_Flash_Tests *)test;

    OspiFlash_ospiClose(ospiObj, pTest->intrPollMode);
    
    return;    
}

static int32_t OspiFlash_DAC_write(uint8_t *buf, uint32_t numBytes)
{
    int32_t             status = OSPI_FLASH_APP_STATUS_SUCCESS;
    uint8_t             *pSrc;         /* Source address */
    uint32_t            i;
    uint8_t             *pDst;         /* Destination address */
    uint32_t            size;
    uint32_t            remainSize;
    uint32_t            wrWord;
    uint32_t            wrByte;
    uint32_t            timeOutVal;
    uint32_t            retry;
    volatile uint32_t   delay;
    uint8_t             statusRegVal;
    uint32_t            regVal;

    const CSL_ospi_flash_cfgRegs *baseAddr = (const CSL_ospi_flash_cfgRegs *)(OSPI_FLASH_CONFIG_REG_BASE_ADDR);

    OspiFlash_ospiXferIntrInit(TRUE);
    
    /* Disable PHY pipeline mode */
    CSL_ospiPipelinePhyEnable((const CSL_ospi_flash_cfgRegs *)(OSPI_FLASH_CONFIG_REG_BASE_ADDR), FALSE);

    
    pSrc = (uint8_t *)buf;
    pDst = (uint8_t *)(OSPI_FLASH_DATA_BASE_ADDR);
    remainSize = (uint32_t)numBytes & 3U;
    size = (uint32_t)numBytes - remainSize;

#ifdef PRINT_WRITE_PERF
    configStopTicks_T1 = OspiFash_getGTCTimerTicks();
    transactionStartTicks_T2 = OspiFash_getGTCTimerTicks();
#endif
    /* Transfer the data in 32-bit size */
    for(i = 0U; i < size; i += 4U)
    {
        wrWord = CSL_REG32_RD(pSrc + i);
        CSL_REG32_WR(pDst + i, wrWord);
        timeOutVal = OSPI_FLASH_WRITE_TIMEOUT;
        statusRegVal = 0xFF;
        while (timeOutVal != 0U)
        {
            (void)CSL_ospiCmdRead(baseAddr, OSPI_FLASH_CMD_RDSR, 1U);
            while(!CSL_ospiIsIdle(baseAddr));
            CSL_ospiFlashExecCmd(baseAddr);
            retry = OSPI_FLASH_WRITE_TIMEOUT;
            while(retry != 0U)
            {
                if(CSL_ospiFlashExecCmdComplete(baseAddr) == TRUE)
                {
                    break;
                }
                delay = OSPI_FLASH_CHECK_IDLE_DELAY;
                while (delay > 0U)
                {  
                    delay = delay - 1U;
                }
                retry--;
            }
            while(!CSL_ospiIsIdle(baseAddr));
            regVal = CSL_REG32_RD(&baseAddr->FLASH_RD_DATA_LOWER_REG);
            (void)memcpy((void *)&statusRegVal, (void *)(&regVal), 1U);
            if ((statusRegVal & 1U) == 0U)
            {
                break;
            }
            timeOutVal--;
            delay = OSPI_FLASH_CHECK_IDLE_DELAY;
            while (delay > 0U)
            {  
                delay = delay - 1U;
            }
        }
    }
    if(OSPI_FLASH_APP_STATUS_SUCCESS == status)
    {
        /* Transfer the remaining data in 8-bit size */
        for(i = 0; i < remainSize; i++)
        {
            wrByte = CSL_REG8_RD(pSrc + size + i);
            CSL_REG8_WR(pDst + size + i, wrByte);
            timeOutVal = OSPI_FLASH_WRITE_TIMEOUT;
            statusRegVal = 0xFF;
            while (timeOutVal != 0U)
            {
                (void)CSL_ospiCmdRead(baseAddr, OSPI_FLASH_CMD_RDSR, 1U);
                while(!CSL_ospiIsIdle(baseAddr));
                CSL_ospiFlashExecCmd(baseAddr);
                retry = OSPI_FLASH_WRITE_TIMEOUT;
                while(retry != 0U)
                {
                    if(CSL_ospiFlashExecCmdComplete(baseAddr) == TRUE)
                    {
                        break;
                    }
                    delay = OSPI_FLASH_CHECK_IDLE_DELAY;
                    while (delay > 0U)
                    {  
                        delay = delay - 1U;
                    }
                    retry--;
                }
                while(!CSL_ospiIsIdle(baseAddr));
                regVal = CSL_REG32_RD(&baseAddr->FLASH_RD_DATA_LOWER_REG);
                (void)memcpy((void *)&statusRegVal, (void *)(&regVal), 1U);
                if ((statusRegVal & 1U) == 0U)
                {
                    break;
                }
                timeOutVal--;
                delay = OSPI_FLASH_CHECK_IDLE_DELAY;
                while (delay > 0U)
                {  
                    delay = delay - 1U;
                }
            }
        }
    }
#ifdef PRINT_WRITE_PERF
    transcationStopTicks_T5 = OspiFash_getGTCTimerTicks();
    
    configTicks = configStopTicks_T1 - configStartTicks_T0  - getTicksDelay;
    configTime = (configTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;
    
    transactionTicks = transcationStopTicks_T5 - transactionStartTicks_T2  - getTicksDelay;
    transactionTime = (transactionTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;

    OSPI_FLASH_log("\n OSPI Write %d bytes complete.\tConfig Time:\t%d ns\tTransaction Time:\t%d ns", numBytes, (uint32_t)configTime, (uint32_t)transactionTime);
#endif

    return status;
}

static int32_t OspiFlash_INDAC_write(App_OspiObj *ospiObj, uint8_t *buf, uint32_t numBytes, bool intrPollMode)
{
    int32_t status = OSPI_FLASH_APP_STATUS_SUCCESS;

#ifdef PRINT_WRITE_PERF
    configStopTicks_T1 = OspiFash_getGTCTimerTicks();
    transactionStartTicks_T2 = OspiFash_getGTCTimerTicks();
#endif

    status = OspiFlash_xspiIndacWrite(ospiObj, buf, numBytes, intrPollMode, 0U);

#ifdef PRINT_WRITE_PERF
    transcationStopTicks_T5 = OspiFash_getGTCTimerTicks();
    
    configTicks = configStopTicks_T1 - configStartTicks_T0  - getTicksDelay;
    configTime = (configTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;
    
    transactionTicks = transcationStopTicks_T5 - transactionStartTicks_T2  - getTicksDelay;
    transactionTime = (transactionTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;

    OSPI_FLASH_log("\n OSPI Write %d bytes complete.\tConfig Time:\t%d ns\tTransaction Time:\t%d ns", numBytes, (uint32_t)configTime, (uint32_t)transactionTime);
#endif

    return status;
}

static int32_t OSPI_waitReadSramLvl(const CSL_ospi_flash_cfgRegs *pReg,
                                    uint32_t *rdLevel)
{
    uint32_t retry = OSPI_FLASH_WRITE_TIMEOUT;
    uint32_t sramLevel;
    int32_t  retVal = OSPI_FLASH_APP_STATUS_SUCCESS;
    volatile uint32_t   delay;

    while(retry != 0U)
    {
        sramLevel = CSL_ospiGetSramLvl(pReg, 1U);
        if (sramLevel != 0U)
        {
            *rdLevel = sramLevel;
            break;
        }
        delay = OSPI_FLASH_CHECK_IDLE_DELAY;
        while (delay > 0U)
            delay = delay - 1U;
        retry--;
    }

    if (retry != 0U)
    {
        retVal = OSPI_FLASH_APP_STATUS_SUCCESS;
    }
    else
    {
        retVal = OSPI_FLASH_APP_STATUS_ERROR;
    }
    return(retVal);
}

static int32_t OSPI_waitIndReadComplete(const CSL_ospi_flash_cfgRegs *pRegs)
{
    uint32_t retry  = OSPI_FLASH_WRITE_TIMEOUT;
    int32_t  retVal = OSPI_FLASH_APP_STATUS_SUCCESS;
    volatile uint32_t   delay;

    /* Check flash indirect read controller status */
    while (retry != 0U)
    {
        if (CSL_ospiIndReadComplete(pRegs) == TRUE)
        {
            break;
        }
        delay = OSPI_FLASH_CHECK_IDLE_DELAY;
        while (delay > 0U)
            delay = delay - 1U;
        retry--;
    }

    if (retry != 0U)
    {
        /* Clear indirect completion status */
        CSL_ospiClrIndReadComplete(pRegs);
        retVal = OSPI_FLASH_APP_STATUS_SUCCESS;
    }
    else
    {
        retVal = OSPI_FLASH_APP_STATUS_ERROR;
    }
    return(retVal);
}

static int32_t OspiFlash_INDAC_read(App_OspiObj *ospiObj, uint8_t *buf, uint32_t numBytes, bool intrPollMode) /* based on OSPI_ind_xfer_mode_read_v0 in OSPI_v0.c */
{
    int32_t             status = OSPI_FLASH_APP_STATUS_SUCCESS;
    uint8_t             *pDst;         /* Destination address */
    uint32_t            size;
    uint32_t            remainSize;
    uint32_t            sramLevel = 0; 
    uint32_t            rdBytes = 0;
    uint32_t            offset = 0; 

    const CSL_ospi_flash_cfgRegs *baseAddr = (const CSL_ospi_flash_cfgRegs *)(OSPI_FLASH_CONFIG_REG_BASE_ADDR);
    pDst = (uint8_t *)buf;
    remainSize = 0;
    size = (uint32_t)numBytes;

    OspiFlash_ospiXferIntrInit(intrPollMode);
    
    /* Disable DAC mode */
    CSL_ospiDacEnable(baseAddr, FALSE);
    /* Set read address in indirect mode */
    CSL_ospiIndSetStartAddr(baseAddr, (uint32_t)offset, TRUE);

#ifdef PRINT_READ_PERF
    configStopTicks_T1 = OspiFash_getGTCTimerTicks();
#endif

    if (intrPollMode)                /* if interrupt mode is used then OSPI_hwiFxn will handle, if poll mode is used the below code will handle */
    {
        /* start the indirect read */
        CSL_ospiIndReadExecute(baseAddr, size);

    #ifdef PRINT_READ_PERF
        transactionStartTicks_T2 = OspiFash_getGTCTimerTicks();
    #endif

        remainSize = size;
        while(remainSize > 0U)
        {
            /* Wait indirect read SRAM fifo has data */
            status = OSPI_waitReadSramLvl(baseAddr, &sramLevel);

            rdBytes = sramLevel * CSL_OSPI_FIFO_WIDTH;
            rdBytes = (rdBytes > remainSize) ? remainSize : rdBytes;

            /* Read data from FIFO */
            CSL_ospiReadFifoData((uintptr_t)(OSPI_FLASH_DATA_BASE_ADDR), pDst, rdBytes);       /* OSPI_FLASH_DATA_BASE_ADDR = MCU_FSS0_DAT_REG1 = 0x0050000000 */

            pDst += rdBytes;
            remainSize -= rdBytes;
        }
        if(status == OSPI_FLASH_APP_STATUS_SUCCESS)
        {
            status = OSPI_waitIndReadComplete(baseAddr);
        }
        if(status == OSPI_FLASH_APP_STATUS_ERROR)
        {
            CSL_ospiIndWriteCancel(baseAddr);
        }
    }
    else
    {
        /* Book keeping of transmit and receive buffers */
        ospiObj->writeBufIdx = NULL_PTR;
        ospiObj->writeCountIdx = 0;
        ospiObj->readBufIdx =  (uint8_t *)rxBuf;
        ospiObj->readCountIdx = (uint32_t)numBytes;

        /* start the indirect read */
        CSL_ospiIndReadExecute(baseAddr, size);

    #ifdef PRINT_READ_PERF
        transactionStartTicks_T2 = OspiFash_getGTCTimerTicks();
    #endif

        /* To wait till read completes in interrupt mode? */
        SemaphoreP_pend(ospiObj->ospiFlashTransferDoneSem, SemaphoreP_WAIT_FOREVER);
    }

#ifdef PRINT_READ_PERF
    transcationStopTicks_T5 = OspiFash_getGTCTimerTicks();
    
    configTicks = configStopTicks_T1 - configStartTicks_T0  - getTicksDelay;
    configTime = (configTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;
    
    transactionTicks = transcationStopTicks_T5 - transactionStartTicks_T2  - getTicksDelay;
    transactionTime = (transactionTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;

    OSPI_FLASH_log("\n OSPI Read %d bytes complete.\tConfig Time:\t%d ns\tTransaction Time:\t%d ns", numBytes, (uint32_t)configTime, (uint32_t)transactionTime);
#endif

    return status;
}

static int32_t OspiFlash_DAC_read(uint8_t *buf, uint32_t numBytes)
{
    int32_t             status = OSPI_FLASH_APP_STATUS_SUCCESS;

    OspiFlash_ospiXferIntrInit(TRUE);

#ifdef PRINT_READ_PERF
    configStopTicks_T1 = OspiFash_getGTCTimerTicks();
    transactionStartTicks_T2 = OspiFash_getGTCTimerTicks();
#endif

    memcpy(buf, (uint8_t *)(OSPI_FLASH_DATA_BASE_ADDR), numBytes);

#ifdef PRINT_READ_PERF
    transcationStopTicks_T5 = OspiFash_getGTCTimerTicks();
    
    configTicks = configStopTicks_T1 - configStartTicks_T0  - getTicksDelay;
    configTime = (configTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;
    
    transactionTicks = transcationStopTicks_T5 - transactionStartTicks_T2  - getTicksDelay;
    transactionTime = (transactionTicks*1000000000U)/(uint64_t)OSPI_FLASH_GTC_CLK_FREQ;

    OSPI_FLASH_log("\n OSPI Read %d bytes complete.\tConfig Time:\t%d ns\tTransaction Time:\t%d ns", numBytes, (uint32_t)configTime, (uint32_t)transactionTime);
#endif

    return status;
}

/*
 *  ======== CompareData ========
 */
static int32_t OspiFlash_verifyData(uint8_t *expData,
                                    uint8_t *rxData,
                                    uint32_t length)
{ 
    uint32_t idx = 0;
    uint32_t match = 1;
    int32_t status = OSPI_FLASH_APP_STATUS_ERROR;

    for(idx = 0; ((idx < length) && (match != 0)); idx++)
    {
        if(*expData != *rxData)
        {
            match = 0;
            OSPI_FLASH_log("Data mismatch at idx %d\n", idx);
        }
        expData++;
        rxData++;
    }

    if(match == 1)
    {
        status = OSPI_FLASH_APP_STATUS_SUCCESS;
    }

    return status;
}

/*
 *  ======== GeneratePattern ========
 */
static void OspiFlash_generatePattern(uint8_t *txBuf, 
                                      uint8_t *rxBuf, 
                                      uint32_t length)
{
    volatile uint32_t idx;
    volatile uint8_t *txPtr = txBuf;
    volatile uint8_t *rxPtr = rxBuf;

    for(idx = 0; idx < length; idx++)
    {
        if(idx < (length/2))
        {
            *txPtr++ = (uint8_t)idx;
        }
        else if(idx < (length/4*3))
        {
            *txPtr++ = 0xaa;
        }
        else
        {
            *txPtr++ = 0x55;
        }
    	*rxPtr++ = (uint8_t)0U;
    }
}

#ifdef UNITY_INCLUDE_CONFIG_H
/*
 *  ======== Unity set up and tear down ========
 */
void setUp(void)
{
    /* Do nothing */
}

void tearDown(void)
{
    /* Do nothing */
}
#endif

void test_csl_ospi_flash_app_runner(void)
{
    /* @description:Test runner for ospi tests

       @requirements: PDK-2408

       @cores: mcu1_0 */
#if defined(UNITY_INCLUDE_CONFIG_H)
    UNITY_BEGIN();
    RUN_TEST (test_csl_ospi_flash_app);
    UNITY_END();
    /* Function to print results defined in our unity_config.h file */
    print_unityOutputBuffer_usingUARTstdio();
#else
    test_csl_ospi_flash_app();
#endif
    return;
}

int main(void)
{
    (void) test_csl_ospi_flash_app_runner();

    while (TRUE)
    {
    }
}
/********************************* End Of File ******************************/

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