TDA4VM: TDA4VM：Questions About LDC DDR Bandwidth Consumption Calculation

shuwan zheng

Prodigy 230 points

Part Number: TDA4VM
Other Parts Discussed in Thread: TEST2

Hi, TI experts,

1. Our TDA4 device using LDC module，convert Image YUV422 uyvy to YUV420 NV21，only using format conversion.

2. Input: 4 sorrond camera data，format YUV422 uyvy，resolution 1280*800，frame rate 30fps

Output: 4 sorrond camera data，format YUV420 NV21，resolution 1280*800，frame rate 30fps

3. Then，based on C66 core format conversion method, using the following calculation, an estimated consumption of around 410MB

read: 1280*800*2*4*30=245,760,000 BYTE，234MB

write: 1280*800*1.5*4*30=184,320,000 BYTE，175MB

4. But, when implementing the functionality with LDC in practice, it was found that the bandwidth consumption is around 580MB, which is 170MB higher.

the LDC params as shown as follows:

5. So, consulting TI experts, is the above calculation incorrect, and how should it be calculated correctly?

over 2 years ago

0 Brijesh Jadav over 2 years ago

TI__Guru**** 484275 points

Hi,

Could you help me understand how you measured LDC BW to be around 580MB/s? Are you using some tool to measure it?

From the LDC parameter perspective, it looks to be fine. You can try increasing block width further to 128 to see if helps. But first need to understand how 580MB/s came?

Regards,

Brijesh

0 shuwan zheng over 2 years ago in reply to Brijesh Jadav

Prodigy 230 points

Hi，

We conducted three tests, obtaining DDR bandwidth values separately, and the LDC difference is 580MB.

Test1: Do not connect 4 surrond cameras, no capture data, DDR bandwith 770MB/S

Test2: Connect 4 surrond cameras, get capture data, but not call LDC function，DDR bandwidth 1020MB/S

Test3: Connect 4 surrond cameras, get capture data, call LDC function and but not using output image data，DDR bandwidth 1600MB/S

So, estimated capturen consumption is around 250MB/s(1020MB/S-770MB/S); estimated LDC consumption is around 580MB/s(1600MB/S-1020MB/S);

The bandwidth consumption for capture is close to the theoretical value（234MB/S）, but the LDC consumption has a significant deviation

0 Brijesh Jadav over 2 years ago in reply to shuwan zheng

TI__Guru**** 484275 points

Hi,

ok, please note that LDC is 2D traffic for both input as well on output side, so i am suspecting it might be affecting. Can you try increasing block width to 128bytes?

Regards,

Brijesh

0 shuwan zheng over 2 years ago in reply to Brijesh Jadav

Prodigy 230 points

Hi,

Are you suggesting changing the fields of outputBlockWidth and outputBlockHeight from 64 to 128?

If yes，can you please explain the impact of these two parameters on bandwidth, or how should the actual bandwidth be calculated?

0 Brijesh Jadav over 2 years ago in reply to shuwan zheng

TI__Guru**** 484275 points

Hi,

yes, more for outputBlockWidth. Please set this to 128 and see if it helps.

Since LDC is 2D traffice, i am just trying to see if having larger read in line helps DDR BW.

Regards,

Brijesh

0 shuwan zheng over 2 years ago in reply to Brijesh Jadav

Prodigy 230 points

Hi,

setting the block parameter to 128 and tesing, the DDR bandwidth decreases by approximately 50MB/s.

so, confused, what is the appropriate value to set for the block?

0 Brijesh Jadav over 2 years ago in reply to shuwan zheng

TI__Guru**** 484275 points

Hi,

You can try to increase it further to value 256., this means more linear access to the DDR and should give more benefit in terms of BW.

Regards,

Brijesh

0 shuwan zheng over 2 years ago in reply to Brijesh Jadav

Prodigy 230 points

Hi， set block value to 256 and LDC report params failed， so the 128 is the max value？

0 Brijesh Jadav over 2 years ago in reply to shuwan zheng

TI__Guru**** 484275 points

With 256 blockheight, you might need to reduce blockHeight? can you reduce blockHeight to half and see if it works?

Regards,

Brijesh

0 Gang Hua over 2 years ago in reply to Brijesh Jadav

TI__Guru 61990 points

OBW is limited up to 248.

So, maybe try 192 (= 64 * 3) instead assuming DDR burst size is 64 bytes.

0 Kangjia Dong over 2 years ago in reply to Gang Hua

TI__Intellectual 2275 points

Hi Gang,

Thanks for your update how to set parameters for decrease DDR bandwidth consumption. But the key question is how to calculate theoretical DDR bandwidth of LDC converting YUV422 to NV12 format? Please help me review the following method whether right?

I try use DCC tool to calculate input DDR bandwidth show as following

The input image YUV422(UYVY) 1280x800 should use 2605504Byte. For customer system should be 2605504x4x30=298MB

The output image NV12 1280x800 should use 1280x800x3/2 = 1536000Byte when block size is 64x64. For customer system should be 1536000x4x30=175.78MB.

0 Gang Hua over 2 years ago in reply to Kangjia Dong

TI__Guru 61990 points

Kangjia Dong said:
But the key question is how to calculate theoretical DDR bandwidth of LDC converting YUV422 to NV12 format? Please help me review the following method whether right?

Yes, tuning tool can do the calculation even though it is not designed for this 422 to 420 conversion.

Theoretically, DDR BW for reading LDC input pixels is 2605504 bytes per frame.

0 Gang Hua over 2 years ago in reply to Gang Hua

TI__Guru 61990 points

To be clear, large block size typically reduces the overhead in DDR reading BW.

Keeping output block width to 64x is good for DDR writing BW.

0 Kangjia Dong over 2 years ago in reply to Gang Hua

TI__Intellectual 2275 points

Hi Gang,

I try use different lut table to load YUV422 image and it will get different DDR bandwidth show as follwoing

This results are different when use different lut tabel

Fullscreen mesh_lut_1280_800.txt Download

  2544   2050
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     0      0
     0      0
    -2      0
    -6      0
   -11      0
   -20      0
   -32      1
   -48      1
   -68      1
   -94      2
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  1826    -41
  1675    -40
  1528    -38
  1388    -36
  1255    -34
  1128    -32
  1008    -30
   895    -28
   789    -26
   691    -24
   600    -22
   516    -20
   439    -18
   370    -16
   308    -15
   253    -13
   204    -11
   162    -10
   126     -8
    95     -7
    70     -5
    49     -4
    33     -3
    21     -2
    12     -1
     6     -1
     2      0
     0      0
     0      0
     0      0
     0      0
     0      0
    -2      0
    -6     -1
   -12     -1
   -20     -2
   -33     -3
   -49     -4
   -69     -5
   -94     -7
  -124     -8
  1830   -104
  1678   -100
  1532    -95
  1392    -90
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   207    -27
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    72    -14
    51    -11
    35     -8
    22     -6
    13     -4
     7     -3
     3     -2
     1     -1
     0      0
     0      0
     0      0
    -1     -1
    -3     -1
    -7     -3
   -13     -4
   -22     -6
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   -50    -11
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  -127    -20

Fullscreen mesh_lut_1280_800_allzero.txt Download

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/UYVY422_5F00_1280x800.yuv

0 Brijesh Jadav over 2 years ago in reply to Kangjia Dong

TI__Guru**** 484275 points

Hi Kangjia,

This is expected because the input size can change based on the Lut, so if you change Lut, the required input BW will change.

I would suggest keeping Lut filled 0 and see what's the input BW.

Regards,

Brijesh

0 Kangjia Dong over 2 years ago in reply to Brijesh Jadav

TI__Intellectual 2275 points

Brijesh,
Customer test result show read bandwidth is 390MB and write bandwidth is 190MB. But according to our theoretical calculation read bandwidth should be 4173312x4X30=477.59MB(Lut filled 0) write bandwidth should be 1536000x4x30=175.78MB. There is a large gap on read bandwidth.

0 Brijesh Jadav over 2 years ago in reply to Kangjia Dong

TI__Guru**** 484275 points

Hi Kangjia,

But how do you/customer measure the individual LDC read and LDC write BW? Are they using some tool to measure each masters BW? Also what else is running in the system when you measure the BW? Are these standalone numbers?

Lets say if you are using Linux on the A72, there might be possible that additional BW is coming due to Linux.

Regards,

Brijesh

0 Gang Hua over 2 years ago in reply to Kangjia Dong

TI__Guru 61990 points

Kangjia Dong said:
But according to our theoretical calculation read bandwidth should be 4173312x4X30=477.59MB(Lut filled 0)

Hi Kangia,

This is what I get from tuning tool.

With 192x32 (0 LUT), DDR read BW = 2425856 bytes per frame (291MB/s).

With 128x32 (0 LUT), DDR read BW = 2584064 bytes per frame (310MB/s).

With 64x64 (0 LUT), DDR read BW = 3066112 bytes per frame (368MB/s).

0 Kangjia Dong over 2 years ago in reply to Gang Hua

TI__Intellectual 2275 points

Hi Gang，
Your shared data is more reasonable than previously shared from me.

64x64 (0 LUT), DDR read BW = 3066112 bytes x 4 x 30=350MB

0 Brijesh Jadav over 2 years ago in reply to Kangjia Dong

TI__Guru**** 484275 points

Hi Kangjia,

ok then, any further question on this ticket?

Regards,

Brijesh

0 Gang Hua over 2 years ago in reply to Brijesh Jadav

TI__Guru 61990 points

Hi Kangia,

This is the tuning tool project I used to calculate the LDC read BW for your reference.

/cfs-file/__key/communityserver-discussions-components-files/791/test_5F00_LDC_5F00_422_5F00_to_5F00_420.7z

You may download the tuning tool from mysecuresw if necessary.

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Processors forum

TDA4VM: TDA4VM：Questions About LDC DDR Bandwidth Consumption Calculation