Part Number: TMDS64GPEVM
Hello,
I'm using PCIE in the following configuration : AM64 RC (A53 Linux) <-> AM64 EP (R5 Baremetal)
My use case : I want EP to act as Bus master and write data buffers directly into RC DDR RAM.
Linux will dynamically allocate some buffers for EP to write into. This can be anywhere in DDR RAM.
This will allow RC to receive large amount of data without CPU usage on it's side (Used for example for network traffic).
How to configure EP outbound translation regions so that EP can write into these dynamically allocated buffers in RC ?
- Do I need to use PCIE0_DAT1 of 4GB ?
If so, is this supported on MCU SDK ? Do I need to use RAT modules ? Is there all drivers necessary for this ?
- Do I need to dynamically define outbound translations for each buffer EP wants to write into ? (This is done in Linux RC to Linux EP example, EP defines outbound regions for each write/read operation done on RC)
If so, Is there some support on MCU sdk for this ?
Thanks
