Other Parts Discussed in Thread: SYSCONFIG,
Using the sysconfig tool, I tried regenerating the evm ddr config. There are only a few differences from the updated tool. I'm curious if any of these changes are important?
$ diff -u arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi ~/projects/am62x/am62_som/k3-am62x-sk-ddr-09.09-config.dtsi --- arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi 2023-10-05 15:09:26.918851143 -0400 +++ /home/jcormier/projects/am62x/am62_som/k3-am62x-sk-ddr-09.09-config.dtsi 2023-10-05 15:03:45.879613040 -0400 @@ -1,18 +1,19 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60 - * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.09 + * Thu Oct 05 2023 15:01:36 GMT-0400 (Eastern Daylight Time) * DDR Type: DDR4 * Frequency = 800MHz (1600MTs) * Density: 16Gb * Number of Ranks: 1 - */ +*/ @@ -334,7 +335,7 @@ -#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_321_DATA 0x00FFFF00 # [23:8] Chip Select Mask 1 - Mask applied to the address decode for chip select 1 @@ -901,7 +902,7 @@ -#define DDRSS_PHY_120_DATA 0x01A00000 +#define DDRSS_PHY_120_DATA 0x01000000 # [25:16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 ?? @@ -1157,7 +1158,7 @@ -#define DDRSS_PHY_376_DATA 0x01A00000 +#define DDRSS_PHY_376_DATA 0x01000000 # [25:16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 @@ -2152,7 +2153,7 @@ -#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 # [17:0] PHY_PAD_CAL_IO_CFG_0 - Pad calibration Controls PCLK/PARK pin and vref switch