Dear expert,
My customer use Jacinto 7 DDRSS configure tools 0.5 version to generator parameters for DDR configuration and find it will has been data bit flips occasionally when read data. So we change 0.5 version to 1.0 version and it work normally now. By the way, we not change the DDR refresh rate on the 1.0 version but it still work. We want to know which change may be impact DDR data bit flips. Could you help explain with more details? Thanks~
0.6.0 "1) Added support for DRA821U
- Added all supported SOC part numbers to parameter A2 (""TI SOC Part Number"") on the ""Config"" tab.
- Added macros to allow user to load the default SDK configurations for DRA821U and DRA829x/TDA4VM. From the ""Title-README"" worksheet, select the desired SOC and then use the ""Load User Config"" button to pre-populate the tool.
* NOTE: Some parameters may be dependent on the selected SOC. Always ensure proper SOC selected when configuring tool."
"2) Enable the DRAM VRCG (errata i2159)
- Register Updates
> DDRSS_PI_259, PI_MR13_DATA_0
> DDRSS_PI_261, PI_MR13_DATA_1
> DDRSS_PI_263, PI_MR13_DATA_2
> DDRSS_PI_265, PI_MR13_DATA_3"
"3) Update PHY PLL SPO calibration control setting to ensure calibration converges to optimal setting
- Register Updates
> DDRSS_PHY_1310, PHY_PLL_SPO_CAL_CTRL"
"4) Reduce the maximum read eye training slave delay search window to reduce boot time
- Register Updates
> DDRSS_PHY_108, PHY_RDLVL_MAX_EDGE_0
> DDRSS_PHY_364, PHY_RDLVL_MAX_EDGE_1
> DDRSS_PHY_620, PHY_RDLVL_MAX_EDGE_2
> DDRSS_PHY_876, PHY_RDLVL_MAX_EDGE_3"
"5) Allow the boot frequency used by drivers to be controlled by tool output.
- Added output parameter DDRSS_PLL_FREQUENCY_0 to worksheets ""u-boot"", ""GEL"", ""RTOS"", ""CMM""
* NOTE: Parameter not used by drivers prior to SDK8.0
6) Modify the default input of parameter A5 (""DDR Memory Boot Frequency"") on the ""Config"" tab to 55 MHz to match max boot frequency supported by DRAM.
- Register updates: No forumlas updated with respect to this update; however, input change will impact several parameter values
* NOTE: This change does not impact the actual boot frequency prior to SDK8.0"
"7) Add 16-bit bus width support
- Added ""16"" bit option of paramter A8 (""DDR Data Bus Width"") on the ""Config"" tab
- Register Updates
> DDRSS_CTL_270, CS_VAL_UPPER_0
> DDRSS_CTL_271, CS_VAL_UPPER_1
> DDRSS_CTL_271, CS_VAL_LOWER_1
> DDRSS_CTL_272, CS_MSK_0
> DDRSS_CTL_273, CS_MSK_1
> DDRSS_CTL_278, REDUC
> DDRSS_CTL_286, DEVICE1_BYTE0_CS0
> DDRSS_CTL_286, MEMDATA_RATIO_0
> DDRSS_CTL_287, DEVICE1_BYTE0_CS1
> DDRSS_CTL_287, DEVICE0_BYTE0_CS1
> DDRSS_CTL_287, MEMDATA_RATIO_1
> DDRSS_PI_14, PI_CS_MAP
> DDRSS_PI_29, PI_WRLVL_CS_MAP
> DDRSS_PI_45, PI_RDLVL_GATE_CS_MAP
> DDRSS_PI_45, PI_RDLVL_CS_MAP
> DDRSS_PI_55, PI_CALVL_CS_MAP
> DDRSS_PI_67, PI_WDQLVL_CS_MAP"
"8) Update controller MR22 parameters to match PI MR22 parameters
- Register Updates
> DDRSS_CTL_181, MR22_DATA_F0_0
> DDRSS_CTL_182, MR22_DATA_F1_0
> DDRSS_CTL_182, MR22_DATA_F2_0
> DDRSS_CTL_189, MR22_DATA_F0_1
> DDRSS_CTL_189, MR22_DATA_F1_1
> DDRSS_CTL_189, MR22_DATA_F2_1"
"9) Update feedback IO settings to use CA input parameters
- Register Updates
> DDRSS_PHY_1406, PHY_PAD_FDBK_DRIVE
> DDRSS_PHY_1407, PHY_PAD_FDBK_DRIVE2"
10) Add "CMM" output tab
0.6.1 "1) Updated write DQ training pattern (from 0x7 to 0x6) to prevent invalid training results observed in some systems
- Register Updates
> DDRSS_PHY_33, PHY_WDQLVL_PATT_0
> DDRSS_PHY_289, PHY_WDQLVL_PATT_1
> DDRSS_PHY_545, PHY_WDQLVL_PATT_2
> DDRSS_PHY_801, PHY_WDQLVL_PATT_3
2) Added a new SDK configuration macro to support the TDA4VM / DRA829x Edge AI board"
0.7.0 "1) Add support for non-power-of-2 density memories
- Added new user options (1Gb, 3Gb, 6Gb, 12Gb) to detail 9 (DDR Density) of section A (System Configuration) on the
Config worksheet
- Register Updates
> DDRSS_CTL_268, ROW_DIFF_0
> DDRSS_CTL_268, ROW_DIFF_1
> DDRSS_CTL_270, CS_VAL_UPPER_0
> DDRSS_CTL_271, CS_VAL_UPPER_1
> DDRSS_CTL_271, CS_VAL_LOWER_1
> DDRSS_CTL_272, CS_MAP_NON_POW2
> DDRSS_CTL_272, ROW_START_VAL_1
> DDRSS_PI_73, PI_ROW_DIFF"
"2) Update register calculation of cs_lower_addr_en for non-power-of-2 density memories (errata i2182)
- Use cs-row-bank-col address mapping with dual-rank non-power-of-2 density LPDDR4 devices
- Register Updates: DDRSS_CTL_273, CS_LOWER_ADDR_EN"
"3) Correct register calculation bug of the tool which impacts the DRAM temperature polling feature
- Description of bug: When temperature polling is enabled and the system temperature gradient is set substantially high relative
to what the processor and DRAM can account for, then the tool calculates a negative time required to read the MR4 register
of the LPDDR4 memory. As a negative value is invalid, this bug results in an incorrect register value and large delay between
reads due to underflow.
- Fix: Updated calculations to program registers to minimum value when system temperature gradient is too large.
- Added a warning to detail 12 (System Temperature Gradient) of section A (System Configuration) on the Config worksheet
when the user inputs a value that results in an invalid value.
- Register Updates
> DDRSS_CTL_124, MRR_TEMPCHK_HIGH_THRESHOLD_F0
> DDRSS_CTL_124, MRR_TEMPCHK_NORM_THRESHOLD_F0
> DDRSS_CTL_125, MRR_TEMPCHK_NORM_THRESHOLD_F1
> DDRSS_CTL_126, MRR_TEMPCHK_HIGH_THRESHOLD_F1
> DDRSS_CTL_127, MRR_TEMPCHK_HIGH_THRESHOLD_F2
> DDRSS_CTL_127, MRR_TEMPCHK_NORM_THRESHOLD_F2"
"4) Add support for TDA4AL, TDA4VE, TDA4VL
a) Add support for second DDRSS
- Duplicate all input parameters with the exception of details 1-4 and 13-15 of section A (System Configuration) on
the Config worksheet
b) Add support for interleaving between two DDR sub-systems
- Changed the name of detail 3 of section A (System Configuration) on the Config worksheet from ""OSC1 Input Frequency""
to ""DDR Controllers Utilized in System"", and added a drop-down selections for parameter.
- Added new inputs, details 13-15 of section A (System Configuration) on the Config worksheet
- Added table section System DDR Size to section A (System Configuration) on the Config worksheet to illustrate memory
usage based on selected parameters
c) Update all output tabs to include items (a) and (b); output for previously supported devices is unchanged when saved using
the push buttons
d) Add macro option to pre-populate tool with inputs for TI EVM / SOM. Update existing device macros for new user inputs."
5) Minor update to save push-buttons to fix file filter for some file types
0.7.1 "1) Fix tool bug that incorrectly used some DDRSS0 inputs to calculate some DDRSS1 register values.
- Register Updates (impacted parameters)
> DDRSS1_CTL_55, BSTLEN
> DDRSS1_CTL_270, CS_VAL_UPPER_0
> DDRSS1_CTL_271, CS_VAL_UPPER_1
> DDRSS1_CTL_271, CS_VAL_LOWER_1
> DDRSS1_CTL_272, CS_MSK_0
> DDRSS1_CTL_273, CS_MSK_1
> DDRSS1_PI_46, PI_TDFI_RDLVL_RR
> DDRSS1_PHY_102, PHY_RDDATA_EN_OE_DLY_0
> DDRSS1_PHY_131, PHY_RDDQS_LATENCY_ADJUST_0
> DDRSS1_PHY_358, PHY_RDDATA_EN_OE_DLY_1
> DDRSS1_PHY_387, PHY_RDDQS_LATENCY_ADJUST_1
> DDRSS1_PHY_614, PHY_RDDATA_EN_OE_DLY_2
> DDRSS1_PHY_643, PHY_RDDQS_LATENCY_ADJUST_2
> DDRSS1_PHY_870, PHY_RDDATA_EN_OE_DLY_3
> DDRSS1_PHY_899, PHY_RDDQS_LATENCY_ADJUST_3"
0.8.0 "1) Improve write DQ training by increasing the minimum valid window to prevent false edge detection.
- NOTE: This change is intended to address the same issue addressed by v0.6.1 (change 1) release.
It is recommended to implement both changes.
- Register Updates (impacted parameters)
> DDRSSn_PHY_32, PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
> DDRSSn_PHY_288, PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
> DDRSSn_PHY_544, PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
> DDRSSn_PHY_800, PHY_WDQLVL_CLK_JITTER_TOLERANCE_3"
"2) Disable the PHY PLL calibration to prevent corner cases where circuit may not lock.
- Register Updates (impacted parameters)
> DDRSSn_PHY_1310, PHY_PLL_SPO_CAL_CTRL"
"3) Enable periodic ZQ calibration of the DRAM.
- Register Updates (impacted parameters)
> DDRSSn_CTL_229, ZQ_CALSTART_HIGH_THRESHOLD_F0
> DDRSSn_CTL_229, ZQ_CALSTART_NORM_THRESHOLD_F0
> DDRSSn_CTL_230, ZQ_CALLATCH_HIGH_THRESHOLD_F0
> DDRSSn_CTL_233, ZQ_CALSTART_NORM_THRESHOLD_F1
> DDRSSn_CTL_234, ZQ_CALLATCH_HIGH_THRESHOLD_F1
> DDRSSn_CTL_234, ZQ_CALSTART_HIGH_THRESHOLD_F1
> DDRSSn_CTL_238, ZQ_CALSTART_HIGH_THRESHOLD_F2
> DDRSSn_CTL_238, ZQ_CALSTART_NORM_THRESHOLD_F2
> DDRSSn_CTL_239, ZQ_CALLATCH_HIGH_THRESHOLD_F2
> DDRSSn_CTL_267, ZQ_CAL_LATCH_MAP_1
> DDRSSn_CTL_267, ZQ_CAL_START_MAP_1
> DDRSSn_CTL_267, ZQ_CAL_LATCH_MAP_0
> DDRSSn_CTL_267, ZQ_CAL_START_MAP_0"
"4) Fix tool bug impacting Read DBI functionality.
- Register Updates (impacted parameters)
> DDRSSn_PHY_102, PHY_DBI_MODE_0
> DDRSSn_PHY_358, PHY_DBI_MODE_1
> DDRSSn_PHY_614, PHY_DBI_MODE_2
> DDRSSn_PHY_870, PHY_DBI_MODE_3"
"5) Enable SOC VREF training
- NOTE: These changes only apply to DRA821. SOC VREF training is already enabled for other parts supported by the tool.
- Register Updates (impacted parameters)
> DDRSS_PI_182, PI_RDLVL_PAT0_EN_F0
> DDRSS_PI_183, PI_RDLVL_PAT0_EN_F1
> DDRSS_PI_184, PI_RDLVL_PAT0_EN_F2"
"6) Updated CA training parameters to improve CA VREF variability
- NOTE: These changes only apply to DRA821
- Register Updates (impacted parameters)
> DDRSSn_PHY_1039, PHY_ADR_CALVL_NUM_PATTERNS_0
> DDRSSn_PHY_1074, PHY_ADR_MEAS_DLY_STEP_ENABLE_0"
"7) Optimized certain training parameters to improve (reduce) the DRAM initialization and training time.
- NOTE: These changes only apply to DRA821, with the exception of PHY_RDLVL_DLY_STEP_* which was updated to match
other supported parts supported by the tool.
- Register Updates (impacted parameters)
> DDRSSn_PI_61, PI_CALVL_VREF_INITIAL_STEPSIZE
> DDRSSn_PI_67, PI_WDQLVL_VREF_INITIAL_STEPSIZE
> DDRSSn_PI_67, PI_WDQLVL_VREF_NORMAL_STEPSIZE
> DDRSSn_PI_72, PI_PARALLEL_WDQLVL_EN
> DDRSSn_PHY_12, PHY_VREF_INITIAL_STEPSIZE_0
> DDRSSn_PHY_268, PHY_VREF_INITIAL_STEPSIZE_1
> DDRSSn_PHY_524, PHY_VREF_INITIAL_STEPSIZE_2
> DDRSSn_PHY_780, PHY_VREF_INITIAL_STEPSIZE_3
> DDRSSn_PHY_31, PHY_RDLVL_CAPTURE_CNT_0
> DDRSSn_PHY_287, PHY_RDLVL_CAPTURE_CNT_1
> DDRSSn_PHY_543, PHY_RDLVL_CAPTURE_CNT_2
> DDRSSn_PHY_799, PHY_RDLVL_CAPTURE_CNT_3
> DDRSSn_PHY_100, PHY_VREF_SETTING_TIME_0
> DDRSSn_PHY_356, PHY_VREF_SETTING_TIME_1
> DDRSSn_PHY_612, PHY_VREF_SETTING_TIME_2
> DDRSSn_PHY_868, PHY_VREF_SETTING_TIME_3
> DDRSSn_PHY_107, PHY_RDLVL_DLY_STEP_0
> DDRSSn_PHY_363, PHY_RDLVL_DLY_STEP_1
> DDRSSn_PHY_619, PHY_RDLVL_DLY_STEP_2
> DDRSSn_PHY_875, PHY_RDLVL_DLY_STEP_3
> DDRSSn_PHY_1073, PHY_ADR_CALVL_DLY_STEP_0
> DDRSSn_PHY_1303, PHY_PLL_WAIT
> DDRSSn_PHY_1397, PHY_CSLVL_DLY_STEP"
"8) Enable single frequency set point to improve (reduce) DRAM initialization and training time.
- NOTE: These changes only apply to DRA821
- Global Updates
> Updated calculation of macro DDRSS_PLL_FHS_CNT
- Register Updates (impacted parameters)
> DDRSSn_PI_12, PI_FREQ_MAP
> DDRSSn_PI_13, PI_INIT_WORK_FREQ
> DDRSSn_PI_176, PI_WRLVL_EN_F2
> DDRSSn_PI_182, PI_RDLVL_GATE_EN_F2
> DDRSSn_PI_182, PI_RDLVL_EN_F2
> DDRSSn_PI_191, PI_CALVL_EN_F2
> DDRSSn_PI_217, PI_WDQLVL_EN_F2"
"9) Update the DRA821 default configuration (macro) to address errata and enable LP4-3200 for SR2.0 material
- ""Config"" Input Updates
> Enable Write DBI (Cells E65, F65, G65)
> Set DDR memory frequency (F2) to 1600 MHz (Cells E33)
- ""DRAMTiming"" Input Updates
> Update read latency to 28 (Cells G25, H25)
> Update write latency to 14 (Cells G27, H27)
> Update write recovery to 30 (Cells G28, H28)
> Update ODTLon to 6 (Cells G29, H29)
> Update ODTLoff to 24 (Cells G30, H30)
- ""IOControl"" Input Updates
> Update CA drive strength to 40 ohms (Cells L27, L28)
> Update CS drive strength to 80 ohms (Cells P27, P28)
- ""RTOS"" Output Updates
> All arrays and macros appended with ""_v1"" and ""_V1"" respectively
> Header file default name appended with ""_v1""."
"10) General Updates
- De-scoped support for DRA821 SR1.0; added support for DRA821 SR2.0
- ""Config"" Worksheet (Section A)
> Removed old table notes 1, 2, 6 (shifting remaining table notes, ex: '3' --> '1')
> Edited table note 1
> Updated detail 9 to state from ""per channel"" to ""per channel for single rank""
- ""Config"" Worksheet (Section B)
> Removed old table notes 2 (shifting remaining table notes, ex: '3' --> '2')"
0.9.0 "1) Fixed tool bug in which the PHY_DBI_MODE parameter of DDRSS1 was previously determined by DDRSS0 tool inputs.
- Register Updates (impacted parameters)
> DDRSS1_PHY_102, PHY_DBI_MODE_0
> DDRSS1_PHY_358, PHY_DBI_MODE_1
> DDRSS1_PHY_614, PHY_DBI_MODE_2
> DDRSS1_PHY_870, PHY_DBI_MODE_3"
2) Fixed tool bug in which the drop down selections for the interleave granularity (Config tab, Section A, Detail 15) were incorrect for non-power-of-2 densities.
"3) Add support for TDA4AH, TDA4AP,TDA4VH, TDA4VP
a) Add support for third and fourth DDRSS
- Duplicate all input parameters with the exception of details 1-4 and 13-15 of section A (System Configuration) on
the Config worksheet
b) Update all output tabs to include items (a); output for previously supported devices is unchanged when saved using
the push buttons
d) Add macro option to pre-populate tool with inputs for TI EVM / SOM."
0.9.1 "1) Fixed tool bug introduced in v0.9.0 in which the MULTI_DDR_CFG_HYBRID_SELECT and MULTI_DDR_CFG_EMIFS_ACTIVE
parameters were assigned the wrong value for the GEL, RTOS, and CMM output tabs."
"2) Re-enable PHY PLL calibration. (Undo change #2 from revision 0.8.0)
- NOTE: This change ONLY applies to J721E devices. PHY PLL calibration disabled for all other devices.
- Register Updates (impacted parameters)
> DDRSSn_PHY_1310, PHY_PLL_SPO_CAL_CTRL"
0.9.2 "1) Reduce the delay caused by write DQ periodic training during normal operation.
- NOTE: These changes only apply to DRA821.
- Register Updates (impacted parameters)
> DDRSSn_PI_66, PI_WDQLVL_ROTATE
> DDRSSn_PI_67, PI_WDQLVL_PERIODIC"
2) Modify the built in macros to set the refresh rate input to 1.95 us (applied to all macros)
0.10.0 1) Update tRASmax to 17.55 us for all default configurations to match the faster refresh rate (1.95 us) applied in v0.9.2 of the tool.
"2) Update the TDA4VE default configuration (macro)
- ""Config"" Input Updates
> Enable Write DBI on both DDRSS (Cells E65, F65, G65, H65, I65, J65)
> Enable Read DBI on DDRSS1 (Cells H64, I64, J64), *which requires modifying the read latency*
- ""DRAMTiming"" Input Updates
> Update DDRSS1 read latency to 40 (Cells I25, J25)
- ""IOControl"" Input Updates
> Update CA ODT to 80 ohms (Cells E79, F79, H79, I79)"
"3) Enable single frequency set point to improve (reduce) DRAM initialization and training time.
- NOTE: This update applies the changes from item number 8 from v0.8.0 of the tool to J721S2 devices.
- Global and Register Updates
> See description of item number 8 from v0.8.0 of the tool."
"4) Optimized certain training parameters to improve (reduce) the DRAM initialization and training time.
- NOTE: This update applies the changes from item number 7 from v0.8.0 of the tool to J721S2 devices, with the exception of
changes to PHY_ADR_CALVL_DLY_STEP_0.
- Register Updates (impacted parameters)
> See description of item number 7 from v0.8.0 of the tool."
"5) Reduce the delay caused by write DQ periodic training during normal operation.
- NOTE: These changes only apply to J721S2 devices and only apply to DDRSS0.
- Register Updates (impacted parameters)
> DDRSS0_PI_66, PI_WDQLVL_ROTATE
> DDRSS0_PI_67, PI_WDQLVL_PERIODIC
> DDRSS0_PHY_33, PHY_WDQLVL_PATT_0
> DDRSS0_PHY_289, PHY_WDQLVL_PATT_1
> DDRSS0_PHY_545, PHY_WDQLVL_PATT_2
> DDRSS0_PHY_801, PHY_WDQLVL_PATT_3"
"6) Adjust the DQS duty cycle
- NOTE: These changes only apply to J721S2 devices.
- Register Updates (impacted parameters)
> DDRSSn_PHY_136, PHY_DATA_DC_DQS_CLK_ADJUST_0
> DDRSSn_PHY_392, PHY_DATA_DC_DQS_CLK_ADJUST_1
> DDRSSn_PHY_648, PHY_DATA_DC_DQS_CLK_ADJUST_2
> DDRSSn_PHY_904, PHY_DATA_DC_DQS_CLK_ADJUST_3"
