Hi Chris,

Thanks for your query.

I will check on this and get back to you by next week.

Best Regards

Ashwani

Hi Chris,

Here are documentation you can refer:

https://software-ndl.ti.com/processor-sdk-linux/esd/AM64X/latest/exports/docs/linux/How_to_Guides/FAQ/How_to_Configure_MSMC_memory.html#how-to-configure-k3-msmc-memory-for-use-as-sram-or-l3-cache

https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/latest/exports/docs/linux/Foundational_Components/PRU-ICSS/Linux_Drivers/PRU_ICSSG_Ethernet.html#sram-requirement

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1236505/faq-am64x-profinet-component-placement-recommendation-for-sitara-mpu-memory

https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/MEMORY_MAP.html

Best Regards

Ashwani

Dear Ashwini ,

I based my question on the literature provided in the two links you shared. Once again, in the third link, it appears that the PRU-ICSSG firmware needs to be directed to MSMC. We intend to load the offload binary to PRU-ICCSSG from Linux, and my concern revolves around how to manage MSMC in AM6442. Unfortunately, I couldn't find any information on MSMC in the TRM of AM6442. Additionally, I want to ensure that PRU-ICCSSG doesn't utilize OCSRAM under any circumstances since, for my application, I plan to allocate most of OCSRAM for critical tasks.

Thank you

Chris

There is no MSMC memory in AM64x, only MSRAM which sometimes is referred to as on-chip RAM (OCRAM). The MSMC FAQ in the documentation applies to J721e and is copied over unnecessarily.

If you use the ICSSG based Ethernet, you will need to allocate the memory as described in https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/latest/exports/docs/linux/Foundational_Components/PRU-ICSS/Linux_Drivers/PRU_ICSSG_Ethernet.html#sram-requirement in MSRAM.

We'll update the documentation to be clearer.

  Pekka

Thanks Pekka,

We need to allocate OCSRAM for both R5F and M4F to support real-time firmware, and it will also serve as a shared memory region between the cores. Consequently, a significant portion of the OCSRAM area must be reserved for this purpose. If ICSSG utilizes OCSRAM, I would like to understand the specific portion it will allocate. Additionally, there is a concern about whether the usage of ICSSG's OCSRAM will impact the overall performance of R5Fs when accessing the OCSRAM.

Thank you

Chris

Thanks Pekka,

I haven't come across any reference node for SRAM other than oc_sram, as you've demonstrated above. Is there an available example of SRAM carveout.  Do we need to allocate the SRAM addresses utilized by R5F and M4F in a manner akin to the example below? Subsequently, the ICCSG firmware will exclusively attempt to access the unallocated portions of the SRAM. Is my interpretation correct?

&cbass_main {
	oc_sram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x00 0x70000000 0x00 0x200000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x00 0x70000000 0x200000>;
		
		/* Reserve 1.25 MB of SRAM for Remote cores */
		device-sram@0x80000 {
		    reg = <0x80000  0x140000>;
		    pool;
		};

		tfa-sram@1c0000 {
			reg = <0x1c0000 0x20000>;
		};

		dmsc-sram@1e0000 {
			reg = <0x1e0000 0x1c000>;
		};

		sproxy-sram@1fc000 {
			reg = <0x1fc000 0x4000>;
		};
	};

Thank you

Chris