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TDA4VM: TDA4VM SDK8.6 MSMC NULL Slave Func failed to write register on MCU3_0

yanggc
Intellectual 470 points
Part Number: TDA4VM

Hello,

    I failed to write to the MSMC NULL Slave function register because I registered an exception check and was prompted to write to address 0x6E005008 DataAbort. I would like to know how to solve this problem?

I tried to read and write the address using the devmem2 command on the A72 terminal, but found that the write failed.

Do I need to modify some content to initiate write operations on this register segment?

  • 0
    TI__Mastermind 19680 points

    Thanks for posting your question to TI processor's E2E forum. The expert assigned to this thread is out of office due to public holidays in India today. Please expect a response by the end of this week.

  • 0 in reply to Fabiana Jaimes
    TI__Guru**** 162570 points

    Hi,

    Some more details on this will help. Which OS? Which SDK version is being used?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 470 points

    Hello,

    Currently, I am using TDA4VM chip SDK8.6,   an exception occurred when writing this register on MCU 3_0.

    The latest progress is that I did not report any errors when writing this register on C7x, but on MCU 1_ 0. MCU 2_ 0. C66x and MCU 3_0 will fail.

  • 0 in reply to yanggc
    Intellectual 470 points

    I want to know why I cannot write to the registers 0x6E000000 to 0x6E00A018 on the core MCU3_0 and can only write to the core C7x. Is this related to the following figure?

    Can I write this register on the core MCU3_0? What settings need to be modified?

  • 0 in reply to yanggc
    TI__Guru**** 162570 points

    Hi,

    The above register space is firewalled. Are you seeing a firewall exception while accessing that from MCU3_0?

    - Keerthy

  • 0 in reply to Keerthy J
    Intellectual 470 points

    Hi,

      I have indeed seen firewall errors in the Log. Can I not operate on these registers?

  • 0 in reply to yanggc
    TI__Guru**** 162570 points

    No. The TIFS firmware restricts these register access. The MCU3_0 will not be able to configure these registers.

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Intellectual 470 points

    Hello,

    I'm sorry for replying to you so late. Can these registers only be modified on core C7x?

  • 0 in reply to Keerthy J
    Intellectual 470 points

    Hi,

        May I know the corresponding firewall ID? Can I reconfigure this section of content?

  • 0 in reply to yanggc
    TI__Guru**** 162570 points

    Hi,

    No it's configured by the sysfw binary. We cannot configure manually.

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    Intellectual 470 points

    Hi,

        Thank you very much for your reply. I have the following questions to inquire about:

        1.Is the null slave event error in MSMC enabled by default or I need to modify the WS register in the following image to enable this function?

        2.Is the NULL Slave in the following figure the same as the appeal content?

  • 0 in reply to yanggc
    TI__Guru**** 162570 points

    Hi Yang,

    I have looped in relevant expert. He will get back on this.

    Best Regards,

    Keerthy 

  • 0 in reply to Keerthy J
    TI__Guru** 120451 points

    Hi Yang,

    MSMC implements a null slave endpoint to handle accesses which cannot be sent to their intended destination

    My understanding is that NULL slave reporting is enabled by default.

    The two TRM sections shown above are both referring to the Null Slave handling in the MSMC.

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 470 points

    Hi,

      I have two more questions to confirm now:

      1. Is the activation of MSMC NULL Slave function controlled through the following registers?

      2. Will be NULL_ Setting SLV Bit to 1 means it is enabled, right? The default value I am currently reading is 0.

  • 0 in reply to yanggc
    TI__Guru** 120451 points

    Hi,

    In testing on target, contrary, to response above the MSMC NULL error reporting is disabled by default.

    Regarding the MSMC_SMIEWS Bit[0], checking with internal team on this.   NULL_SLV Bit[0] is a 'W' only bit, its read back value will not have any meaning.   

    The MSMC_SMIESTAT Bit[0], should reflect the current state of the enable.

    Checking with SDK team for support of MSMC Null Slave error detection, will response no later that EOD Nov. 10th.

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 470 points

    Hi，

    When I obtain the status, it is the MSMC that I read_ SMIESTAT register. Actually, in the chip manual, MSMC_ SMIESTAT and MSMC_SMIEWS the register addresses are the same.The value I obtained when reading MSMC_SMIESTAT [0] is 0, so I believe this feature is not enabled.

    How should I enable this feature?

  • 0 in reply to yanggc
    TI__Guru** 120451 points

    Yes, understood, as per response above, TI is checking with TI SDK team for support of MSMC Null Slave error detection, will response no later that EOD Nov. 10th.

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 470 points

    Hi，

    Thank you very much and look forward to your reply.

    In addition to the appealed MSMC NULL Slave issue, there are also some functional safety issues in the figure below that I would like to consult.

    The document  "SPRUIR1-DRA829_TDA4VM_Safety_ManualF5_draft_Auto.pdf" states that the MSMC3.INT4- Error codes for invalid transactions feature is already enabled by default, so:

    1. How can I proactively insert invalid bus transactions to trigger an error?

    2. How can I obtain the error message after triggering it? Are there registers with storage errors available for reading and writing? Will it still trigger certain interrupts?

    < Pictures Removed>

  • +1 in reply to yanggc
    TI__Guru** 120451 points

    Hi,

    Some updates on the NULL Slave Error

    • The detection of a NULL Slave Error is always enabled by H/W, no S/W interaction is required.  
      • How the error is handled on the originating core, is a function of that core.  For example the A72 QNX would likely generate a SIGBUS.
      • I have not tested the Null reporting before, but expectation is that if a valid address range in the device memory map is accessed, where the memory being accessed does not have a corresponding H/W module, the Null reporting module would be hit.  
    • The logging/reporting of the Null slave error as you have noted is required to be enabled by S/W
      • The Null Slave Error reporting is not enabled by default in the TI SDKs
      • There in an internal discussion on TI side on enablement of this feature.

    Please be aware that the TI Safety Manual is only available under NDA, portions of the above thread have been modified accordingly.

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 470 points

    Hi,

    Thank you very much for your reply. I understand the issue with NULL Slave.

    I would like to ask how to detect the safety of the Interconnect function of MSMC mentioned above?

  • 0 in reply to yanggc
    Intellectual 470 points

    add a picture about my issue

  • +1 in reply to yanggc
    TI__Guru** 120451 points

    My high level understanding is that an access to a memory address, that is valid in regard to being in the range of the supported memory map, but not assigned to a H/W module would trigger the Null Slave.   Take a look at the Memory Map definitions in the TRM Section 2.   An access to a gap in the memory map should hit the NULL slave.

    The requesting core would be informed of the failed access, functionality would depend on the core from which the access was done and the OS which is present there.   For example, an access from A72 QNX as described above would result in a SIGBUS.

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 470 points

    Hello,

    Thank you for your answer regarding NULL Slave. I have already understood the function of NULL Slave. I would like to ask another interconnect question about MSMC now:

    The document  "SPRUIR1-DRA829_TDA4VM_Safety_ManualF5_draft_Auto.pdf" states that the MSMC3.INT4- Error codes for invalid transactions feature is already enabled by default, so:

    1. How can I proactively insert invalid bus transactions to trigger an error?

    2. How can I obtain the error message after triggering it? Are there registers with storage errors available for reading and writing? Will it still trigger certain interrupts?