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Using a DSPs memory interface to interface with a high speed ADC

uofastudent
Prodigy 70 points

Other Parts Discussed in Thread: ADS5485

I want to interface a high speed ADC such as the ADS5485 with a relatively low power DSP. The ADS5485 has LDVS, DDR output signaling. There are 8 differential signals carrying the data and one differential signal that can be used to clock in the data. The data is updated on both the rising and falling edge of the clock.

A very powerful DSP that consumes a lot of power may also be useful if it has ultra low power sleep modes.

Can a DSP DDR memory interface be used in this way or almost in this way with minimal additional circuitry such as tri-state devices so that a memory can still be accessed?

  • 0
    TI__Mastermind 42545 points

    I think it's unlikely you could get this to work.  It appears that the sampling is constant based on the clock.  You would need some logic to buffer the samples and allow them to be read in bursts similar to a DDR memory access.  You would probably have better luck placing an FPGA between the ADS5485 and the DSP.  You could build the logic to collect the samples from the ADS5485 and buffer them into a structure that could be transferred to the DSP.  You could then use one of the DSPs serial interfaces, such as McBSP or SRIO, to transfer the data from the FPGA to the DSP.  This would be simpler the trying to splice the DDR interface to the ADS5485.