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TDA4VL-Q1: Stuck on DSS initialization via HDMI

Quanfeng Fu
Intellectual 325 points

Part Number: TDA4VL-Q1

Hi TI experts,

HW: our custom board

SDK: j721s2, 8.6

I want to enable HDMI output on own board. The program is stuck when call Dss_evtMgrRegister() function.  How to resolve it?

The whole log is below:

[MCU2_0] 2.181810 s: CIO: Init ... Done !!!
[MCU2_0] 2.181873 s: ### CPU Frequency = 1000000000 Hz
[MCU2_0] 2.181933 s: fqf: DSS Board_pinmuxUpdate status 0 !!!
[MCU2_0] 2.181968 s: CPU is running FreeRTOS
[MCU2_0] 2.181991 s: APP: Init ... !!!
[MCU2_0] 2.182014 s: SCICLIENT: Init ... !!!
[MCU2_0] 2.182161 s: SCICLIENT: DMSC FW version [8.6.3--1-g2249f (Chill Capybara]
[MCU2_0] 2.182198 s: SCICLIENT: DMSC FW revision 0x8
[MCU2_0] 2.182229 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_0] 2.182263 s: SCICLIENT: Init ... Done !!!
[MCU2_0] 2.182289 s: UDMA: Init ... !!!
[MCU2_0] 2.183240 s: UDMA: Init ... Done !!!
[MCU2_0] 2.183281 s: UDMA: Init ... !!!
[MCU2_0] 2.183802 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0] 2.183866 s: MEM: Init ... !!!
[MCU2_0] 2.183907 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d5000000 of size 16777216 bytes !!!
[MCU2_0] 2.183978 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 60000000 of size 262144 bytes !!!
[MCU2_0] 2.184036 s: MEM: Init ... Done !!!
[MCU2_0] 2.184060 s: IPC: Init ... !!!
[MCU2_0] 2.184116 s: IPC: 5 CPUs participating in IPC !!!
[MCU2_0] 2.184156 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0] 10.665818 s: IPC: HLOS is ready !!!
[MCU2_0] 10.678321 s: IPC: Init ... Done !!!
[MCU2_0] 10.678379 s: APP: Syncing with 4 CPUs ... !!!
[MCU2_0] 11.370367 s: APP: Syncing with 4 CPUs ... Done !!!
[MCU2_0] 11.370410 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0] 11.371759 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0] 11.371804 s: FVID2: Init ... !!!
[MCU2_0] 11.371863 s: FVID2: Init ... Done !!!
[MCU2_0] 11.371890 s: SCICLIENT: Sciclient_pmSetModuleState module=219 state=2
[MCU2_0] 11.372049 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 11.372100 s: DSS: Init ... !!!
[MCU2_0] 11.372125 s: DSS: Display type is HDMI !!!
[MCU2_0] 11.372152 s: DSS: M2M Path is enabled !!!
[MCU2_0] 11.372179 s: DSS: SoC init ... !!!
[MCU2_0] 11.372202 s: SCICLIENT: Sciclient_pmSetModuleState module=158 state=0
[MCU2_0] 11.372286 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0] 11.372320 s: SCICLIENT: Sciclient_pmSetModuleClkParent module=158 clk=5 parent=7
[MCU2_0] 11.372520 s: SCICLIENT: Sciclient_pmSetModuleClkParent success
[MCU2_0] 11.372612 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=158 clk=5 freq=45000000
[MCU2_0] 11.403891 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0] 11.403928 s: SCICLIENT: Sciclient_pmModuleClkRequest module=158 clk=5 state=2 flag=0
[MCU2_0] 11.404164 s: SCICLIENT: Sciclient_pmModuleClkRequest success
[MCU2_0] 11.404197 s: DSS: SoC init ... Done !!!
[MCU2_0] 11.404222 s: DSS: Board init ... !!!
[MCU2_0] 11.404246 s: DSS: Board init ... Done !!!
[MCU2_0] 11.404273 s: fqf: appDssInit !!!
[MCU2_0] 11.404316 s: src/drv/common/dss_init.c @ Line 109:
[MCU2_0] 11.404347 s: fqf Dss_fillSocInfo
[MCU2_0] 11.404528 s: src/drv/common/dss_init.c @ Line 125:
[MCU2_0] 11.404560 s: Dss_dctrlDrvInit
[MCU2_0] 11.404808 s: src/drv/dctrl/dss_dctrlApi.c @ Line 222:
[MCU2_0] 11.404894 s: Dss_dispDrvInit 111
[MCU2_0] 11.405322 s: src/drv/dctrl/dss_dctrlApi.c @ Line 226:
[MCU2_0] 11.405357 s: Dss_dispDrvInit 222
[MCU2_0] 11.405405 s: src/drv/dctrl/dss_dctrlApi.c @ Line 241:
[MCU2_0] 11.405435 s: Dss_dispDrvInit 333
[MCU2_0] 11.405475 s: src/drv/dctrl/dss_dctrlApi.c @ Line 265:
[MCU2_0] 11.405506 s: Dss_dispDrvInit 444
[MCU2_0] 11.405540 s: src/drv/dctrl/dss_dctrlApi.c @ Line 278:
[MCU2_0] 11.405574 s: Dss_dispDrvInit aaa 0
[MCU2_0] 11.405605 s: src/drv/dctrl/dss_dctrlApi.c @ Line 282:
[MCU2_0] 11.405638 s: Dss_dispDrvInit bbb 0
[MCU2_0] 11.405669 s: src/drv/dctrl/dss_dctrlApi.c @ Line 287:
[MCU2_0] 11.405702 s: Dss_dispDrvInit ccc 0
[MCU2_0] 11.405736 s: src/drv/common/dss_evtMgr.c @ Line 271:
[MCU2_0] 11.405771 s: Dss_evtMgrRegister 111 instId 0
[MCU2_0] 11.405805 s: src/drv/common/dss_evtMgr.c @ Line 282:
[MCU2_0] 11.405839 s: Dss_evtMgrRegister 111 instId 0
[MCU2_0] 11.405872 s: src/drv/common/dss_evtMgr.c @ Line 286:
[MCU2_0] 11.405906 s: Dss_evtMgrRegister 222 instId 0
[MCU2_1] 2.172253 s: CIO: Init ... Done !!!
[MCU2_1] 2.172317 s: ### CPU Frequency = 1000000000 Hz
[MCU2_1] 2.172352 s: CPU is running FreeRTOS
[MCU2_1] 2.172376 s: APP: Init ... !!!
[MCU2_1] 2.172398 s: SCICLIENT: Init ... !!!
[MCU2_1] 2.172541 s: SCICLIENT: DMSC FW version [8.6.3--1-g2249f (Chill Capybara]
[MCU2_1] 2.172580 s: SCICLIENT: DMSC FW revision 0x8
[MCU2_1] 2.172610 s: SCICLIENT: DMSC FW ABI revision 3.1
[MCU2_1] 2.172644 s: SCICLIENT: Init ... Done !!!
[MCU2_1] 2.172672 s: UDMA: Init ... !!!
[MCU2_1] 2.173822 s: UDMA: Init ... Done !!!
[MCU2_1] 2.173883 s: MEM: Init ... !!!
[MCU2_1] 2.173922 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d6000000 of size 16777216 bytes !!!
[MCU2_1] 2.173988 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 60040000 of size 262144 bytes !!!
[MCU2_1] 2.174046 s: MEM: Init ... Done !!!
[MCU2_1] 2.174071 s: IPC: Init ... !!!
[MCU2_1] 2.174124 s: IPC: 5 CPUs participating in IPC !!!
[MCU2_1] 2.174165 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_1] 11.357916 s: IPC: HLOS is ready !!!
[MCU2_1] 11.370276 s: IPC: Init ... Done !!!
[MCU2_1] 11.370325 s: APP: Syncing with 4 CPUs ... !!!
[MCU2_1] 11.370367 s: APP: Syncing with 4 CPUs ... Done !!!
[MCU2_1] 11.370402 s: REMOTE_SERVICE: Init ... !!!
[MCU2_1] 11.371902 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_1] 11.371946 s: FVID2: Init ... !!!
[MCU2_1] 11.372003 s: FVID2: Init ... Done !!!
[MCU2_1] 11.372029 s: VHWA: DMPAC: Init ... !!!
[MCU2_1] 11.372054 s: SCICLIENT: Sciclient_pmSetModuleState module=58 state=2
[MCU2_1] 11.372201 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1] 11.372235 s: SCICLIENT: Sciclient_pmSetModuleState module=62 state=2
[MCU2_1] 11.372474 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_1] 11.372507 s: VHWA: DOF Init ... !!!
[MCU2_1] 11.407517 s: VHWA: DOF Init ... Done !!!
[MCU2_1] 11.407565 s: VHWA: SDE Init ... !!!
[MCU2_1] 11.408997 s: VHWA: SDE Init ... Done !!!
[MCU2_1] 11.409038 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_1] 11.409081 s: VX_ZONE_INIT:Enabled
[MCU2_1] 11.409108 s: VX_ZONE_ERROR:Enabled
[MCU2_1] 11.409134 s: VX_ZONE_WARNING:Enabled
[MCU2_1] 11.410520 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target MCU2-1
[MCU2_1] 11.410733 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_SDE
[MCU2_1] 11.410933 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:66] Added target DMPAC_DOF
[MCU2_1] 11.410985 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[MCU2_1] 11.411020 s: APP: OpenVX Target kernel init ... !!!
[MCU2_1] 11.411303 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_1] 11.411338 s: UDMA Copy: Init ... !!!
[MCU2_1] 11.412384 s: UDMA Copy: Init ... Done !!!
[MCU2_1] 11.412439 s: APP: Init ... Done !!!
[MCU2_1] 11.412468 s: APP: Run ... !!!
[MCU2_1] 11.412492 s: IPC: Starting echo test ...
[MCU2_1] 11.414588 s: APP: Run ... Done !!!
[MCU2_1] 11.415200 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C7X_1[P] C7X_2[.]
[MCU2_1] 11.415327 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[s] C7X_1[P] C7X_2[P]
[C7x_1 ] 2.495199 s: CIO: Init ... Done !!!
[C7x_1 ] 2.495225 s: ### CPU Frequency = 500000000 Hz
[C7x_1 ] 2.495246 s: CPU is running FreeRTOS
[C7x_1 ] 2.495263 s: APP: Init ... !!!
[C7x_1 ] 2.495277 s: SCICLIENT: Init ... !!!
[C7x_1 ] 2.495418 s: SCICLIENT: DMSC FW version [8.6.3--1-g2249f (Chill Capybara]
[C7x_1 ] 2.495446 s: SCICLIENT: DMSC FW revision 0x8
[C7x_1 ] 2.495465 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_1 ] 2.495486 s: SCICLIENT: Init ... Done !!!
[C7x_1 ] 2.495504 s: UDMA: Init ... !!!
[C7x_1 ] 2.496534 s: UDMA: Init ... Done !!!
[C7x_1 ] 2.496556 s: MEM: Init ... !!!
[C7x_1 ] 2.496576 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ db000000 of size 335544320 bytes !!!
[C7x_1 ] 2.496617 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000001) @ 70020000 of size 3964928 bytes !!!
[C7x_1 ] 2.496653 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 64800000 of size 458752 bytes !!!
[C7x_1 ] 2.496688 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 64e00000 of size 16384 bytes !!!
[C7x_1 ] 2.496721 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ d7000000 of size 67108864 bytes !!!
[C7x_1 ] 2.496758 s: MEM: Init ... Done !!!
[C7x_1 ] 2.496774 s: IPC: Init ... !!!
[C7x_1 ] 2.496799 s: IPC: 5 CPUs participating in IPC !!!
[C7x_1 ] 2.496824 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ] 10.055825 s: IPC: HLOS is ready !!!
[C7x_1 ] 10.058232 s: IPC: Init ... Done !!!
[C7x_1 ] 10.058256 s: APP: Syncing with 4 CPUs ... !!!
[C7x_1 ] 11.370369 s: APP: Syncing with 4 CPUs ... Done !!!
[C7x_1 ] 11.370403 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ] 11.370698 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ] 11.370738 s: VX_ZONE_INIT:Enabled
[C7x_1 ] 11.370758 s: VX_ZONE_ERROR:Enabled
[C7x_1 ] 11.370777 s: VX_ZONE_WARNING:Enabled
[C7x_1 ] 11.371092 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1
[C7x_1 ] 11.371210 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_2
[C7x_1 ] 11.371316 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_3
[C7x_1 ] 11.371421 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_4
[C7x_1 ] 11.371527 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_5
[C7x_1 ] 11.371638 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_6
[C7x_1 ] 11.371746 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_7
[C7x_1 ] 11.371853 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP_C7-1_PRI_8
[C7x_1 ] 11.371895 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_1 ] 11.371920 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ] 11.372180 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ] 11.372205 s: APP: Init ... Done !!!
[C7x_1 ] 11.372222 s: APP: Run ... !!!
[C7x_1 ] 11.372238 s: IPC: Starting echo test ...
[C7x_1 ] 11.372434 s: APP: Run ... Done !!!
[C7x_1 ] 11.405194 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C7X_1[s] C7X_2[P]
[C7x_1 ] 11.415324 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C7X_1[s] C7X_2[P]
[C7x_2 ] 2.725063 s: CIO: Init ... Done !!!
[C7x_2 ] 2.725089 s: ### CPU Frequency = 500000000 Hz
[C7x_2 ] 2.725111 s: CPU is running FreeRTOS
[C7x_2 ] 2.725127 s: APP: Init ... !!!
[C7x_2 ] 2.725143 s: SCICLIENT: Init ... !!!
[C7x_2 ] 2.725286 s: SCICLIENT: DMSC FW version [8.6.3--1-g2249f (Chill Capybara]
[C7x_2 ] 2.725313 s: SCICLIENT: DMSC FW revision 0x8
[C7x_2 ] 2.725333 s: SCICLIENT: DMSC FW ABI revision 3.1
[C7x_2 ] 2.725355 s: SCICLIENT: Init ... Done !!!
[C7x_2 ] 2.725372 s: UDMA: Init ... !!!
[C7x_2 ] 2.726387 s: UDMA: Init ... Done !!!
[C7x_2 ] 2.726410 s: MEM: Init ... !!!
[C7x_2 ] 2.726429 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ ef000000 of size 16777216 bytes !!!
[C7x_2 ] 2.726469 s: MEM: Created heap (L2_MEM, id=2, flags=0x00000001) @ 65800000 of size 458752 bytes !!!
[C7x_2 ] 2.726505 s: MEM: Created heap (L1_MEM, id=3, flags=0x00000001) @ 65e00000 of size 16384 bytes !!!
[C7x_2 ] 2.726539 s: MEM: Created heap (DDR_SCRATCH_MEM, id=4, flags=0x00000001) @ f0000000 of size 67108864 bytes !!!
[C7x_2 ] 2.726576 s: MEM: Init ... Done !!!
[C7x_2 ] 2.726593 s: IPC: Init ... !!!
[C7x_2 ] 2.726616 s: IPC: 5 CPUs participating in IPC !!!
[C7x_2 ] 2.726642 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_2 ] 10.573077 s: IPC: HLOS is ready !!!
[C7x_2 ] 10.575502 s: IPC: Init ... Done !!!
[C7x_2 ] 10.575528 s: APP: Syncing with 4 CPUs ... !!!
[C7x_2 ] 11.370369 s: APP: Syncing with 4 CPUs ... Done !!!
[C7x_2 ] 11.370399 s: REMOTE_SERVICE: Init ... !!!
[C7x_2 ] 11.370715 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_2 ] 11.370752 s: VX_ZONE_INIT:Enabled
[C7x_2 ] 11.370772 s: VX_ZONE_ERROR:Enabled
[C7x_2 ] 11.370791 s: VX_ZONE_WARNING:Enabled
[C7x_2 ] 11.371628 s: VX_ZONE_INIT:[tivxPlatformCreateTargetId:59] Added target DSP-1
[C7x_2 ] 11.371670 s: VX_ZONE_INIT:[tivxInitLocal:130] Initialization Done !!!
[C7x_2 ] 11.371696 s: APP: OpenVX Target kernel init ... !!!
[C7x_2 ] 11.372180 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_2 ] 11.372208 s: UDMA Copy: Init ... !!!
[C7x_2 ] 11.404483 s: UDMA Copy: Init ... Done !!!
[C7x_2 ] 11.404509 s: APP: Init ... Done !!!
[C7x_2 ] 11.404527 s: APP: Run ... !!!
[C7x_2 ] 11.404542 s: IPC: Starting echo test ...
[C7x_2 ] 11.404769 s: APP: Run ... Done !!!
[C7x_2 ] 11.405211 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[x] C7X_1[P] C7X_2[s]
[C7x_2 ] 11.415344 s: IPC: Echo status: mpu1_0[x] mcu2_0[x] mcu2_1[P] C7X_1[P] C7X_2[s]

Thanks

Regards

quanfeng

  • 0
    TI__Guru**** 504165 points

    Hi,

    Do you mean HDMI output? Because there is not HDMI output from DSS and the one available in the SDK is not really validated on J721S2. 

    Can you please go further to check where it crashes or hangs? 

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 325 points

    Hi Brijesh,

    Thanks for your reply

    When I add the following code, the HDMI output works.

    SET_DEVICE_STATE_ON(TISCI_DEV_DSS0);
    Regards,

    quanfeng

  • 0 in reply to Quanfeng Fu
    TI__Guru**** 504165 points

    Hi quanfeng,

    Could you help me understand where you have added this statement to get HDMI working? 

    Regards,

    Brijesh

  • +1 in reply to Brijesh Jadav
    Intellectual 325 points

    Hi Brijesh,

    Here is the patch to fix hdmi output.

    diff --git a/ti-processor-sdk-rtos-j721s2-evm-08_06_01_03/vision_apps/utils/dss/src/app_dss_soc.c b/ti-processor-sdk-rtos-j721s2-evm-08_06_01_03/vision_apps/utils/dss/src/app_dss_soc.c
index 3066bb89cd..39ef6b9fde 100755
--- a/ti-processor-sdk-rtos-j721s2-evm-08_06_01_03/vision_apps/utils/dss/src/app_dss_soc.c
+++ b/ti-processor-sdk-rtos-j721s2-evm-08_06_01_03/vision_apps/utils/dss/src/app_dss_soc.c
@@ -226,9 +226,11 @@ void appDssConfigurePm(app_dss_default_prm_t *prm)
      * Therefore, set parent to PLL19 HSDIV0 and then set rate
      * to 148.5 MHz
      */
+        SET_DEVICE_STATE_OFF(TISCI_DEV_DSS0);
         SET_CLOCK_PARENT(TISCI_DEV_DSS0, TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK, TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0);
         SET_CLOCK_FREQ (TISCI_DEV_DSS0, TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK, prm->timings.pixelClock);
         SET_CLOCK_STATE(TISCI_DEV_DSS0, TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK, 0, TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ);
+        SET_DEVICE_STATE_ON(TISCI_DEV_DSS0);
     }
     else if (prm->display_type==APP_DSS_DEFAULT_DISPLAY_TYPE_DSI)
     {

    Regards,

    quanfeng

  • +1 in reply to Quanfeng Fu
    TI__Guru**** 504165 points

    Thanks quanfeng, got it. This was just missing for the HDMI output. For DSI and eDP outputs, i see it is enabled. 

    I have raised this issue to our team and will be fixed in the next release.

    https://jira.itg.ti.com/browse/TIOVX-1416

     

    Regards,

    Brijesh