AM6442: MCU_SPI0 usage

Kanae

All processors and DMA have the physical path to read from and write to any memory mapped end points listed in the SoC memory map, so there is no connectivity issue.

If you are crossing interconnect domains, there may be additional latency, see figure 3-1 in the TRM (Rev H).

Do all SPIs need to use all the available CS?  

--Paul 

Hi Paul,

Thank yo for your reply.

All SPI's want to use all available CS's, but would consider reducing them.

Am I correct in understanding that the latest version of TRM is (Rev G)?
www.ti.com/.../spruim2g.pdf

Best Regards,
Kanae

Hi Paul,

Thank yo for your support

I will  share the latest TRM with my customer.

Regarding the following question from you, as per my previous post,
all SPIs would like to use all available CSs, but I am considering reducing them.

paul said;
Do all SPIs need to use all the available CS?  

Are there any problems or concerns with using all CSs?

Best Regards,
Kanae

Kanae said:

Are there any problems or concerns with using all CSs?

No concerns, Just make sure it is understood that using all CS signals is not a requirement for the device. 

Hi Paul,

Thank you for your support.

I will share it with my customer.

Best Regards,
Kanae