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DM365/DMAV2 - AEMIF 8-bit/16-bit interface

Elvis Mota
Prodigy 200 points
Other Parts Discussed in Thread: TMS320DM365

Hello,

I have taken over a design that uses the TMS320DM365 device. Currently, The AEMIF interface is only connected to an on-board NAND Flash using an 8-bit bus.

Previous designer states that 16-bit bus is provided in the main interface connector of this design for future development (EM_CE1).

Although the AECFG[2:0] lines are available to be configured for either 8-bit or 16-bit bus, terminal EM_BA1/GIO66/KEYB1/HINTN (bga ID R17) in not provided.

I assume this is a problem when trying to address 16-bit memory devices. Am I correct or I'm missing something?

Regards and thank you for your feedback.

 

Elvis Mota

  • 0
    TI__Expert 4510 points

    Hi Elvis,

     

    I am not sure if I understand your question completely.

    If you look at the AEMIF, it can support both 8-bit and 16-bit option. The input pins AECFG[2:0] as you mention determine the AEMIF configuration immediately after reset. On DM365 EVM, we have connected it to NAND Flash in 8-bit mode. If you want to use 16-bit connection, you would need to change the AECFG[2:0] pins in hardware to support 16-bit configuration as per Section 3.7.5 Page 67 of DM365 datasheet. The maximum number of address lines pins in 16-bit mode are 23 which include EM_BA[1] + EM_A[0:13]+ EM_BA[0] (as pin A[14]) + EM_A[15:20] + EM_A[21]. Do note you would need to change PinMux4 register appropriately to make some of these pins available after reset.

    As Table 3-14 Page 68 suggest EM_BA[1] would be available only in 16-bit mode configuration when you set AECFG[2:0] to 001, 010, 101 or 110.

    Please let me know if further clarification is needed.

    Prateek

     

  • 0 in reply to Prateek Bansal
    TI__Expert 4510 points

    Question from the customer -

    I have a few more questions.

    I’m confused about, “As Table 3-14 Page 68 suggest EM_BA[1] would be available only in 16-bit mode configuration when you set AECFG[2:0] to 001, 010, 101 or 110.”

    Wouldn’t setting AECFG[2:0] to either 001 or 010 (AECFG[2] = 0) configure the AEMIF to 8-bit mode?

     

    My other question is:

    Is the function of the AECFG[2:0] pins to determine the AEMIF mode operation right after RESET only for BOOTSTRAP access to NAND via EMIF?

    What I mean is:

    -          Assume DMVA2 boots from on-board NAND Flash (8-bit data bus)

    -          AECFG[2:0] hard-wired (pull-down resistors) for such setup (000)

    -          Once the DMVA2 AEMIF is asserted to 8-bit mode at boot up, can it be reasserted to 16-bit mode without a RESET (another device that uses 16-bit mode connected to second AEMIF chip select)?

    -          8-bit or 16-bit mode is not set PER address space, is this correct?

    I might be confusing the AEMIF data bus width with its configuration of address space.

     

    Another question is:

    In 8-bit mode, is the data driven onto both halves of the bus?

  • 0 in reply to Prateek Bansal
    TI__Expert 4510 points

    Wouldn’t setting AECFG[2:0] to either 001 or 010 (AECFG[2] = 0) configure the AEMIF to 8-bit mode?

    <PB> Yes, you are correct. AECFG[2] = 0 implies 8-bit EMIF configuration and AECFG[2] = 1 implies 16-bit EMIF configuration. So, 101 and 110 settings would allow for 16-bit mode configuration and make EM_BA[x] bits available. Apologize for confusion before.

     

    My other question is:

    Is the function of the AECFG[2:0] pins to determine the AEMIF mode operation right after RESET only for BOOTSTRAP access to NAND via EMIF?

    What I mean is:

    -          Assume DMVA2 boots from on-board NAND Flash (8-bit data bus)

    -          AECFG[2:0] hard-wired (pull-down resistors) for such setup (000)

    -          Once the DMVA2 AEMIF is asserted to 8-bit mode at boot up, can it be reasserted to 16-bit mode without a RESET (another device that uses 16-bit mode connected to second AEMIF chip select)?

    -          8-bit or 16-bit mode is not set PER address space, is this correct?

    I might be confusing the AEMIF data bus width with its configuration of address space.

     

    <PB> The AECFG[2:0] bits are sampled on EM_A[10:8] (Table 3-12 Page 64) bits at the time of reset. This sampled values are stored in last 3 bits of BOOTCFG register as specified on Page 130 Section 9.12.7 of ARM Subsystem Reference Guide (link).  As you will see all these values are read only bits. So, the AECFG[2:0] bit values can't be changed after reset - they have to be sampled at boot up time. As such, changing from 8-bit to 16-bit mode after reset would not be possible. Alternative to this would be to use boot mode other than NAND boot mode and then move to 16-bit AEMIF configuration following this. Also, note 16-bit NAND boot mode is not supported. What do you plan to connect to device via 16-bit mode?

    Another question is:

    In 8-bit mode, is the data driven onto both halves of the bus?

    <PB> My understanding is it is not. In 8-bit mode, EM_D[8:15] pins are available as GPIO as per Table 85 - Page 131 of ARM Subsystem reference guide and as such data is only available on EM_D[7:0] pins.