PROCESSOR-SDK-J721S2: PROCESSOR-SDK-J721S2

I have cross checked the memory map and linker command files are ok. created the kernel images and optee image accordingly.

C7X, A72 images based on the memory map changes are working fine. Only when loading the Main R5F this issue is observed. Looks some memory map issue, 

[ 4.967694] remoteproc remoteproc2: attaching to 41000000.r5f
[ 4.973530] platform 41000000.r5f: R5F core initialized in IPC-only mode
[ 4.980224] remoteproc2#vdev0buffer: assigned reserved memory node vision-apps-r5f-dma-memory@a0000000
[ 4.989830] virtio_rpmsg_bus virtio2: rpmsg host is online
[ 4.995336] remoteproc2#vdev0buffer: registered virtio2 (type 7)
[ 5.001417] remoteproc remoteproc2: remote processor 41000000.r5f is now attached
[ 5.013151] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0x1e
[ 5.020454] virtio_rpmsg_bus virtio2: creating channel rpmsg_chrdev addr 0xe
[ 5.027767] platform 5c00000.r5f: R5F core may have been powered on by a different host, programmed state (0) != actual state (1)
[ 5.039676] platform 5c00000.r5f: configured R5F for IPC-only mode
[ 5.045929] platform 5c00000.r5f: assigned reserved memory node vision-apps-r5f-dma-memory@a2000000
[ 5.055489] remoteproc remoteproc3: 5c00000.r5f is available
[ 5.061170] remoteproc remoteproc3: attaching to 5c00000.r5f
[ 5.066832] Unable to handle kernel paging request at virtual address ffff800021ffffff
[ 5.074732] Mem abort info:
[ 5.077515] ESR = 0x96000007
[ 5.080560] EC = 0x25: DABT (current EL), IL = 32 bits
[ 5.085858] SET = 0, FnV = 0
[ 5.088905] EA = 0, S1PTW = 0
[ 5.092048] Data abort info:
[ 5.094922] ISV = 0, ISS = 0x00000007
[ 5.098744] CM = 0, WnR = 0
[ 5.101701] swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000080fc8000
[ 5.108387] [ffff800021ffffff] pgd=00000000fffff003, p4d=00000000fffff003, pud=00000000ffffe003, pmd=0000000083300003, pte=0000000000000000
[ 5.120889] Internal error: Oops: 96000007 [#1] PREEMPT SMP
[ 5.126444] Modules linked in: ti_k3_r5_remoteproc(+) ti_k3_dsp_remoteproc rpmsg_kdrv_switch virtio_rpmsg_bus rpmsg_pru rpmsg_char
[ 5.138167] CPU: 1 PID: 168 Comm: insmod Not tainted 5.10.162-g76b3e88d56 #1
[ 5.145195] Hardware name: Texas Instruments J721S2 EVM (DT)
[ 5.150838] pstate: 00000005 (nzcv daif -PAN -UAO -TCO BTYPE=--)
[ 5.156834] pc : rproc_handle_resources.constprop.0+0x94/0x168
[ 5.162651] lr : rproc_boot+0x334/0x670
[ 5.166472] sp : ffff80001167b790
[ 5.169773] x29: ffff80001167b790 x28: ffff0000032314e8
[ 5.175069] x27: ffff000003231000 x26: ffffffffffffffff
[ 5.180366] x25: ffff800022000000 x24: ffff800010efd8a8
[ 5.185662] x23: ffff000003231038 x22: 0000000000000000
[ 5.190958] x21: ffff80001129cfa0 x20: ffff000003231000
[ 5.196253] x19: 0000000000000000 x18: 0000000000000010
[ 5.201549] x17: 0000000000000000 x16: 0000000000000000
[ 5.206845] x15: ffff0000033b8550 x14: ffffffffffffffff
[ 5.212142] x13: ffffffffffffffff x12: ffffffffffffffff
[ 5.217438] x11: ffffffffffffffff x10: ffffffffffffffff
[ 5.222735] x9 : ffffffffffffffff x8 : ffffffffffffffff
[ 5.228031] x7 : ffffffffffffffff x6 : ffff0000033ff600
[ 5.233327] x5 : 0000000000000000 x4 : 0000000000000000
[ 5.238623] x3 : 00000000000000fd x2 : 00000000ffffffff
[ 5.243919] x1 : ffff800022000003 x0 : ffff800022000000
[ 5.249216] Call trace:
[ 5.251652] rproc_handle_resources.constprop.0+0x94/0x168
[ 5.257120] rproc_boot+0x334/0x670
[ 5.260595] rproc_add+0x88/0x158
[ 5.263903] k3_r5_probe+0x720/0xdb8 [ti_k3_r5_remoteproc]
[ 5.269374] platform_drv_probe+0x54/0xa8
[ 5.273368] really_probe+0xec/0x3e0
[ 5.276929] driver_probe_device+0x58/0xb8
[ 5.281011] device_driver_attach+0x74/0x80
[ 5.285179] __driver_attach+0x64/0xf8
[ 5.288915] bus_for_each_dev+0x70/0xc0
[ 5.292737] driver_attach+0x24/0x30
[ 5.296298] bus_add_driver+0x150/0x200
[ 5.300120] driver_register+0x64/0x120
[ 5.303942] __platform_driver_register+0x48/0x58
[ 5.308631] k3_r5_rproc_driver_init+0x20/0x1000 [ti_k3_r5_remoteproc]
[ 5.315141] do_one_initcall+0x54/0x1b8
[ 5.318965] do_init_module+0x44/0x1f0
[ 5.322701] load_module+0x1f08/0x24a8
[ 5.326436] __do_sys_finit_module+0xb8/0xf8
[ 5.330691] __arm64_sys_finit_module+0x20/0x30
[ 5.335209] el0_svc_common.constprop.0+0x78/0x1c8
[ 5.339984] do_el0_svc+0x24/0x90
[ 5.343286] el0_svc+0x14/0x20
[ 5.346329] el0_sync_handler+0xb0/0xb8
[ 5.350149] el0_sync+0x180/0x1c0
[ 5.353453] Code: 128002b3 9121c021 97ffeb45 1400002e (b87a6b20)
[ 5.359530] ---[ end trace 590125883e204713 ]---
Segmentation fault

Hi Sivaguru,

Can you please respond with the additional details requested below:

• SDK version?
• Is this a custom board or TI EVM?
• What is the boot flow? Using SPL or sbl to boot?

Best Regards,

Keerthy 

Hi Keerthy,

SDK version : 8.6 (8.6.1.3), TDA4 Mid Eco J721S2 board usibg SBL boot.

PMIC -> BIST -> DMSC Init -> MCU R5F SBL -> Load Sysfw -> R5F MCU / loads boot App  -> A72, DSP & Main R5F cores.

I am unable to root login after my memory map changes. Now there is no failure in resource table but there is no prints from the R5F terminal which means there is no handshake between A72 and R5F. Kindly guide me where i can suspect the problem?

Hello,

Allow me some time to check the log and reply back.

Regards

Tarun Mukesh

Hello,

Is it working by default without memory map changes ? if so can you also share me the changes you did the vision apps memory app to reproduce at my end.

Regards

Tarun Mukesh

#ifndef APP_MEM_MAP_H
#define APP_MEM_MAP_H


/* Main OCRAM for MCU2_0 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_0_ADDR (0x03600000u)
#define MAIN_OCRAM_MCU2_0_SIZE (0x00040000u)

/* Main OCRAM for MCU2_1 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_1_ADDR (0x03640000u)
#define MAIN_OCRAM_MCU2_1_SIZE (0x00040000u)

/* L2 for C7x_1 [ size 448.00 KB ] */
#define L2RAM_C7x_1_ADDR (0x64800000u)
#define L2RAM_C7x_1_SIZE (0x00070000u)

/* L1 for C7x_1 [ size 16.00 KB ] */
#define L1RAM_C7x_1_ADDR (0x64E00000u)
#define L1RAM_C7x_1_SIZE (0x00004000u)

/* L2 for C7x_2 [ size 448.00 KB ] */
#define L2RAM_C7x_2_ADDR (0x65800000u)
#define L2RAM_C7x_2_SIZE (0x00070000u)

/* L1 for C7x_2 [ size 16.00 KB ] */
#define L1RAM_C7x_2_ADDR (0x65E00000u)
#define L1RAM_C7x_2_SIZE (0x00004000u)

/* MSMC for C7x_1 [ size  3.78 MB ] */
#define MSMC_C7x_1_ADDR (0x70020000u)
#define MSMC_C7x_1_SIZE (0x003C8000u)

/* DDR for MCU1_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU1_0_IPC_ADDR (0xA0000000u)
#define DDR_MCU1_0_IPC_SIZE (0x00100000u)

/* DDR for MCU1_0 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU1_0_DTS_ADDR (0xA0100000u)
#define DDR_MCU1_0_DTS_SIZE (0x00F00000u)

/* DDR for MCU1_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU1_1_IPC_ADDR (0xA1000000u)
#define DDR_MCU1_1_IPC_SIZE (0x00100000u)

/* DDR for MCU1_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU1_1_DTS_ADDR (0xA1100000u)
#define DDR_MCU1_1_DTS_SIZE (0x00F00000u)

/* DDR for MCU2_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU2_0_IPC_ADDR (0xA2000000u)
#define DDR_MCU2_0_IPC_SIZE (0x00100000u)

/* DDR for MCU2_0 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_MCU2_0_DTS_ADDR (0xA2100000u)
#define DDR_MCU2_0_DTS_SIZE (0x01F00000u)

/* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU2_1_IPC_ADDR (0xA4000000u)
#define DDR_MCU2_1_IPC_SIZE (0x00100000u)

/* DDR for MCU2_1 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_MCU2_1_DTS_ADDR (0xA4100000u)
#define DDR_MCU2_1_DTS_SIZE (0x01F00000u)

/* DDR for MCU3_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU3_0_IPC_ADDR (0xA6000000u)
#define DDR_MCU3_0_IPC_SIZE (0x00100000u)

/* DDR for MCU3_0 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU3_0_DTS_ADDR (0xA6100000u)
#define DDR_MCU3_0_DTS_SIZE (0x00F00000u)

/* DDR for MCU3_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU3_1_IPC_ADDR (0xA7000000u)
#define DDR_MCU3_1_IPC_SIZE (0x00100000u)

/* DDR for MCU3_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU3_1_DTS_ADDR (0xA7100000u)
#define DDR_MCU3_1_DTS_SIZE (0x00F00000u)

/* DDR for C7x_2 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C7x_2_IPC_ADDR (0xA8000000u)
#define DDR_C7x_2_IPC_SIZE (0x00100000u)

/* DDR for C7x_2 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_C7x_2_DTS_ADDR (0xA8100000u)
#define DDR_C7x_2_DTS_SIZE (0x01F00000u)

/* DDR for C7x_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C7x_1_IPC_ADDR (0xAA000000u)
#define DDR_C7x_1_IPC_SIZE (0x00100000u)

/* DDR for C7x_1 for all sections, used for reserving memory in DTS file [ size 111.00 MB ] */
#define DDR_C7x_1_DTS_ADDR (0xAA100000u)
#define DDR_C7x_1_DTS_SIZE (0x06F00000u)

/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define IPC_VRING_MEM_ADDR (0xB2000000u)
#define IPC_VRING_MEM_SIZE (0x02000000u)

/* Memory for remote core logging [ size 256.00 KB ] */
#define APP_LOG_MEM_ADDR (0xB4000000u)
#define APP_LOG_MEM_SIZE (0x00040000u)

/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 52.22 MB ] */
#define TIOVX_OBJ_DESC_MEM_ADDR (0xB4040000u)
#define TIOVX_OBJ_DESC_MEM_SIZE (0x03438000u)

/* Memory for lpc shared memory. MUST be non-cached or cache-coherent [ size  4.62 MB ] */
#define LPC_SHARED_MEM_ADDR (0xB7478000u)
#define LPC_SHARED_MEM_SIZE (0x004A0000u)

/* Memory for global timer memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define GLOBAL_TIMER_MEM_ADDR (0xB7918000u)
#define GLOBAL_TIMER_MEM_SIZE (0x00020000u)

/* Memory for vip shared buf memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define VIP_SHARED_BUF_MEM_ADDR (0xB7938000u)
#define VIP_SHARED_BUF_MEM_SIZE (0x00020000u)

/* Memory for validate info memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define VALIDATE_INFO_MEM_ADDR (0xB7958000u)
#define VALIDATE_INFO_MEM_SIZE (0x00020000u)

/* Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define TIOVX_LOG_RT_MEM_ADDR (0xB7978000u)
#define TIOVX_LOG_RT_MEM_SIZE (0x02000000u)

/* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
#define DDR_SHARED_MEM_ADDR (0xB9978000u)
#define DDR_SHARED_MEM_SIZE (0x20000000u)

/* DDR for MCU1_0 for local heap [ size  8.00 MB ] */
#define DDR_MCU1_0_LOCAL_HEAP_ADDR (0xD9978000u)
#define DDR_MCU1_0_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU1_1 for local heap [ size  8.00 MB ] */
#define DDR_MCU1_1_LOCAL_HEAP_ADDR (0xDA178000u)
#define DDR_MCU1_1_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU2_0 local heap for tiovx use [ size  8.00 MB ] */
#define DDR_MCU2_0_LOCAL_HEAP_TIOVX_ADDR (0xDA978000u)
#define DDR_MCU2_0_LOCAL_HEAP_TIOVX_SIZE (0x00800000u)

/* DDR for MCU2_0 local heap for normal use [ size  8.00 MB ] */
#define DDR_MCU2_0_LOCAL_HEAP_NORMAL_ADDR (0xDB178000u)
#define DDR_MCU2_0_LOCAL_HEAP_NORMAL_SIZE (0x00800000u)

/* DDR for MCU2_1 local heap for tiovx use [ size  8.00 MB ] */
#define DDR_MCU2_1_LOCAL_HEAP_TIOVX_ADDR (0xDB978000u)
#define DDR_MCU2_1_LOCAL_HEAP_TIOVX_SIZE (0x00800000u)

/* DDR for MCU2_1 local heap for normal use [ size  8.00 MB ] */
#define DDR_MCU2_1_LOCAL_HEAP_NORMAL_ADDR (0xDC178000u)
#define DDR_MCU2_1_LOCAL_HEAP_NORMAL_SIZE (0x00800000u)

/* DDR for MCU3_0 for local heap [ size  8.00 MB ] */
#define DDR_MCU3_0_LOCAL_HEAP_ADDR (0xDC978000u)
#define DDR_MCU3_0_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU3_1 for local heap [ size  8.00 MB ] */
#define DDR_MCU3_1_LOCAL_HEAP_ADDR (0xDD178000u)
#define DDR_MCU3_1_LOCAL_HEAP_SIZE (0x00800000u)

/* Main OCRAM Physical Address for MCU2_0 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_0_PHYS_ADDR (0x4F02000000u)
#define MAIN_OCRAM_MCU2_0_PHYS_SIZE (0x00040000u)

/* Main OCRAM Physical Address for MCU2_1 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_1_PHYS_ADDR (0x4F02040000u)
#define MAIN_OCRAM_MCU2_1_PHYS_SIZE (0x00040000u)

#define DDR_64BIT_BASE_VADDR (0x100000000u)
#define DDR_64BIT_BASE_PADDR (0x880000000u)

#endif /* APP_MEM_MAP_H */

Dtsi memory 

 
 /* 
  * IMPORTANT NOTE: Follow below instructions to apply the updated memory map to linux dtsi file, 
  * 
  * 1. Copy the memory sections, from the generated dts file, to the file shown below under reserved_memory: reserved-memory { ... } 
  *     ${LINUX_KERNEL_PATH}/arch/arm64/boot/dts/ti/k3-j721s2-rtos-memory-map.dtsi
  * 
  * 2. Rebuild the dtb, dtbo from PSDK Linux install directory 
  *      make linux-dtbs 
  * 
  * 3. Install the dtb, dtbo to the rootfs/boot folder on SD card 
  *      sudo make linux-dtbs_intall; sync 
  * 
   */


	mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa0000000 0x00 0x00100000>;
		no-map;
	};
	mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa0100000 0x00 0x00f00000>;
		no-map;
	};
	mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa1000000 0x00 0x00100000>;
		no-map;
	};
	mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa1100000 0x00 0x00f00000>;
		no-map;
	};
	main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa2000000 0x00 0x00100000>;
		no-map;
	};
	main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa2100000 0x00 0x01f00000>;
		no-map;
	};
	main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a4000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa4000000 0x00 0x00100000>;
		no-map;
	};
	main_r5fss0_core1_memory_region: r5f-memory@a4100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa4100000 0x00 0x01f00000>;
		no-map;
	};
	main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a6000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa6000000 0x00 0x00100000>;
		no-map;
	};
	main_r5fss1_core0_memory_region: r5f-memory@a6100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa6100000 0x00 0x00f00000>;
		no-map;
	};
	main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a7000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa7000000 0x00 0x00100000>;
		no-map;
	};
	main_r5fss1_core1_memory_region: r5f-memory@a7100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa7100000 0x00 0x00f00000>;
		no-map;
	};
	c71_1_dma_memory_region: c71_1-dma-memory@a8000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa8000000 0x00 0x00100000>;
		no-map;
	};
	c71_1_memory_region: c71_1-memory@a8100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa8100000 0x00 0x01f00000>;
		no-map;
	};
	c71_0_dma_memory_region: c71-dma-memory@aa000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xaa000000 0x00 0x00100000>;
		no-map;
	};
	c71_0_memory_region: c71_0-memory@aa100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xaa100000 0x00 0x06f00000>;
		no-map;
	};
	rtos_ipc_memory_region: rtos-ipc-memory-region@b2000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xb2000000 0x00 0x02000000>;
		no-map;
	};
	memory_region: dma-memory@b4000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xb4000000 0x00 0x05978000>;
		no-map;
	};
	shared_region: shared-memories {
		compatible = "dma-heap-carveout";
		reg = <0x00 0xb9978000 0x00 0x20000000>;
	};
	core_heaps_lo: core-heap-memory-lo@d9978000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xd9978000 0x00 0x04000000>;
		no-map;
	};
	core_heaps_hi: core-heap-memory-hi@880000000 {
		compatible = "shared-dma-pool";
		reg = <0x08 0x80000000 0x00 0x2e000000>;
		no-map;
	};

Its 2GB DDR configuration.

I could see the remoteproc for each core is created and attached along with virtio is created for each cores on the main domain from A72.

MCU boot also looks fine.

Do we have any option to make sure what are the cores running and its status? how to make sure the core utilization memory? How to add prints in linker command file? 

Hello,

/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define IPC_VRING_MEM_ADDR (0xB2000000u)
#define IPC_VRING_MEM_SIZE (0x02000000u)

/* Memory for remote core logging [ size 256.00 KB ] */
#define APP_LOG_MEM_ADDR (0xB4000000u)
#define APP_LOG_MEM_SIZE (0x00040000u)

/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 52.22 MB ] */
#define TIOVX_OBJ_DESC_MEM_ADDR (0xB4040000u)
#define TIOVX_OBJ_DESC_MEM_SIZE (0x03438000u)

/* Memory for lpc shared memory. MUST be non-cached or cache-coherent [ size 4.62 MB ] */
#define LPC_SHARED_MEM_ADDR (0xB7478000u)
#define LPC_SHARED_MEM_SIZE (0x004A0000u)

/* Memory for global timer memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define GLOBAL_TIMER_MEM_ADDR (0xB7918000u)
#define GLOBAL_TIMER_MEM_SIZE (0x00020000u)

/* Memory for vip shared buf memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define VIP_SHARED_BUF_MEM_ADDR (0xB7938000u)
#define VIP_SHARED_BUF_MEM_SIZE (0x00020000u)

/* Memory for validate info memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define VALIDATE_INFO_MEM_ADDR (0xB7958000u)
#define VALIDATE_INFO_MEM_SIZE (0x00020000u)

/* Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define TIOVX_LOG_RT_MEM_ADDR (0xB7978000u)
#define TIOVX_LOG_RT_MEM_SIZE (0x02000000u)

Here If i calculate the size here , it is around ~123MB.

Intially in the mpu cfg file , we have 2GB DDR space as cacheable and we will make 128MB Non cacheable starting from VRING MEM ADDRESS .Please check your j721s2_mpu_cfg.c file , if it is still 128MB then it is wrong you need to modify to the address which is as above. As remaining ~5MB has to be cacheable.

Regards

Tarun Mukesh

#ifndef MEM_MAP_H
#define MEM_MAP_H


/* Main OCRAM for MCU2_0 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_0_ADDR (0x03600000u)
#define MAIN_OCRAM_MCU2_0_SIZE (0x00040000u)

/* Main OCRAM for MCU2_1 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_1_ADDR (0x03640000u)
#define MAIN_OCRAM_MCU2_1_SIZE (0x00040000u)

/* L2 for C7x_1 [ size 448.00 KB ] */
#define L2RAM_C7x_1_ADDR (0x64800000u)
#define L2RAM_C7x_1_SIZE (0x00070000u)

/* L1 for C7x_1 [ size 16.00 KB ] */
#define L1RAM_C7x_1_ADDR (0x64E00000u)
#define L1RAM_C7x_1_SIZE (0x00004000u)

/* L2 for C7x_2 [ size 448.00 KB ] */
#define L2RAM_C7x_2_ADDR (0x65800000u)
#define L2RAM_C7x_2_SIZE (0x00070000u)

/* L1 for C7x_2 [ size 16.00 KB ] */
#define L1RAM_C7x_2_ADDR (0x65E00000u)
#define L1RAM_C7x_2_SIZE (0x00004000u)

/* MSMC for C7x_1 [ size  3.78 MB ] */
#define MSMC_C7x_1_ADDR (0x70020000u)
#define MSMC_C7x_1_SIZE (0x003C8000u)

/* DDR for MCU1_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU1_0_IPC_ADDR (0xA0000000u)
#define DDR_MCU1_0_IPC_SIZE (0x00100000u)

/* DDR for MCU1_0 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU1_0_DTS_ADDR (0xA0100000u)
#define DDR_MCU1_0_DTS_SIZE (0x00F00000u)

/* DDR for MCU1_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU1_1_IPC_ADDR (0xA1000000u)
#define DDR_MCU1_1_IPC_SIZE (0x00100000u)

/* DDR for MCU1_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU1_1_DTS_ADDR (0xA1100000u)
#define DDR_MCU1_1_DTS_SIZE (0x00F00000u)

/* DDR for MCU2_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU2_0_IPC_ADDR (0xA2000000u)
#define DDR_MCU2_0_IPC_SIZE (0x00100000u)

/* DDR for MCU2_0 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_MCU2_0_DTS_ADDR (0xA2100000u)
#define DDR_MCU2_0_DTS_SIZE (0x01F00000u)

/* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU2_1_IPC_ADDR (0xA4000000u)
#define DDR_MCU2_1_IPC_SIZE (0x00100000u)

/* DDR for MCU2_1 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_MCU2_1_DTS_ADDR (0xA4100000u)
#define DDR_MCU2_1_DTS_SIZE (0x01F00000u)

/* DDR for MCU3_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU3_0_IPC_ADDR (0xA6000000u)
#define DDR_MCU3_0_IPC_SIZE (0x00100000u)

/* DDR for MCU3_0 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU3_0_DTS_ADDR (0xA6100000u)
#define DDR_MCU3_0_DTS_SIZE (0x00F00000u)

/* DDR for MCU3_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU3_1_IPC_ADDR (0xA7000000u)
#define DDR_MCU3_1_IPC_SIZE (0x00100000u)

/* DDR for MCU3_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU3_1_DTS_ADDR (0xA7100000u)
#define DDR_MCU3_1_DTS_SIZE (0x00F00000u)

/* DDR for C7x_2 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C7x_2_IPC_ADDR (0xA8000000u)
#define DDR_C7x_2_IPC_SIZE (0x00100000u)

/* DDR for C7x_2 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_C7x_2_DTS_ADDR (0xA8100000u)
#define DDR_C7x_2_DTS_SIZE (0x01F00000u)

/* DDR for C7x_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C7x_1_IPC_ADDR (0xAA000000u)
#define DDR_C7x_1_IPC_SIZE (0x00100000u)

/* DDR for C7x_1 for all sections, used for reserving memory in DTS file [ size 111.00 MB ] */
#define DDR_C7x_1_DTS_ADDR (0xAA100000u)
#define DDR_C7x_1_DTS_SIZE (0x06F00000u)

/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define IPC_VRING_MEM_ADDR (0xB2000000u)
#define IPC_VRING_MEM_SIZE (0x02000000u)

/* Memory for remote core logging [ size 256.00 KB ] */
#define APP_LOG_MEM_ADDR (0xB4000000u)
#define APP_LOG_MEM_SIZE (0x00040000u)

/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 58.50 MB ] */
#define TIOVX_OBJ_DESC_MEM_ADDR (0xB4040000u)
#define TIOVX_OBJ_DESC_MEM_SIZE (0x03A80000u)

/* Memory for lpc shared memory. MUST be non-cached or cache-coherent [ size  5.25 MB ] */
#define LPC_SHARED_MEM_ADDR (0xB7AC0000u)
#define LPC_SHARED_MEM_SIZE (0x00540000u)

/* Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define TIOVX_LOG_RT_MEM_ADDR (0xB8000000u)
#define TIOVX_LOG_RT_MEM_SIZE (0x02000000u)

/* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
#define DDR_SHARED_MEM_ADDR (0xBA000000u)
#define DDR_SHARED_MEM_SIZE (0x20000000u)

/* DDR for MCU1_0 for local heap [ size  8.00 MB ] */
#define DDR_MCU1_0_LOCAL_HEAP_ADDR (0xDA000000u)
#define DDR_MCU1_0_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU1_1 for local heap [ size  8.00 MB ] */
#define DDR_MCU1_1_LOCAL_HEAP_ADDR (0xDA800000u)
#define DDR_MCU1_1_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU2_0 local heap for tiovx use [ size  8.00 MB ] */
#define DDR_MCU2_0_LOCAL_HEAP_TIOVX_ADDR (0xDB000000u)
#define DDR_MCU2_0_LOCAL_HEAP_TIOVX_SIZE (0x00800000u)

/* DDR for MCU2_0 local heap for normal use [ size  8.00 MB ] */
#define DDR_MCU2_0_LOCAL_HEAP_NORMAL_ADDR (0xDB800000u)
#define DDR_MCU2_0_LOCAL_HEAP_NORMAL_SIZE (0x00800000u)

/* DDR for MCU2_1 local heap for tiovx use [ size  8.00 MB ] */
#define DDR_MCU2_1_LOCAL_HEAP_TIOVX_ADDR (0xDC000000u)
#define DDR_MCU2_1_LOCAL_HEAP_TIOVX_SIZE (0x00800000u)

/* DDR for MCU2_1 local heap for normal use [ size  8.00 MB ] */
#define DDR_MCU2_1_LOCAL_HEAP_NORMAL_ADDR (0xDC800000u)
#define DDR_MCU2_1_LOCAL_HEAP_NORMAL_SIZE (0x00800000u)

/* DDR for MCU3_0 for local heap [ size  8.00 MB ] */
#define DDR_MCU3_0_LOCAL_HEAP_ADDR (0xDD000000u)
#define DDR_MCU3_0_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU3_1 for local heap [ size  8.00 MB ] */
#define DDR_MCU3_1_LOCAL_HEAP_ADDR (0xDD800000u)
#define DDR_MCU3_1_LOCAL_HEAP_SIZE (0x00800000u)

/* Main OCRAM Physical Address for MCU2_0 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_0_PHYS_ADDR (0x4F02000000u)
#define MAIN_OCRAM_MCU2_0_PHYS_SIZE (0x00040000u)

/* Main OCRAM Physical Address for MCU2_1 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_1_PHYS_ADDR (0x4F02040000u)
#define MAIN_OCRAM_MCU2_1_PHYS_SIZE (0x00040000u)

#define DDR_64BIT_BASE_VADDR (0x100000000u)
#define DDR_64BIT_BASE_PADDR (0x880000000u)

#endif /* APP_MEM_MAP_H */

Hello,

Please confirm that you are using "gen_linker_mem_map.py" to generate the files and later you are copying the data into linux k3-j721s2-rtos-memory-map.dtsi file and giving build , replacing respective .dtbo file.

Could you share me the .dtbo file after replacing ?

Sivaguru Subramanian said:

Dtsi memory 

The .dtsi file which you shared looks to be k3-j721s2-som-p0.dtsi but not  k3-j721s2-rtos-memory-map.dtsi , Could you please verify? As you are using vision apps , you need to modify in the corresponding memory map file.

Regards

Tarun Mukesh

Hello Tarun,

We have an overlay file to update the memory node on top of  k3-j721s2-rtos-memory-map.dtsi and yes I am updating the gen_linker_mem_map.py and generating the memmap and k3-j721s2-rtos-memory-map.dtsi .

I updated the k3-j721s2-rtos-memory-map.dtsi  changes to k3-j721s2-rtos-memory-map-overlay.dtsi which will considered as reserved memory section.

k3-j721s2-vision-apps.dtbo is generated and check its matching with the reserved memory section.

k3-j721s2-rtos-memory-map-overlay.dtsi below

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;

	vision_apps_mcu_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a0000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa0000000 0x00 0x100000>;
		no-map;
	};
	vision_apps_mcu_r5fss0_core0_memory_region: vision-apps-r5f-memory@a0100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa0100000 0x00 0xf00000>;
		no-map;
	};
	vision_apps_mcu_r5fss0_core1_dma_memory_region: vision-apps-r5f-dma-memory@a1000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa1000000 0x00 0x100000>;
		no-map;
	};
	vision_apps_mcu_r5fss0_core1_memory_region: vision-apps-r5f-memory@a1100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa1100000 0x00 0xf00000>;
		no-map;
	};
	vision_apps_main_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a2000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa2000000 0x00 0x100000>;
		no-map;
	};
	vision_apps_main_r5fss0_core0_memory_region: vision-apps-r5f-memory@a2100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa2100000 0x00 0x1f00000>;
		no-map;
	};
	vision_apps_main_r5fss0_core1_dma_memory_region: vision-apps-r5f-dma-memory@a4000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa4000000 0x00 0x100000>;
		no-map;
	};
	vision_apps_main_r5fss0_core1_memory_region: vision-apps-r5f-memory@a4100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa4100000 0x00 0x1f00000>;
		no-map;
	};
	vision_apps_main_r5fss1_core0_dma_memory_region: vision-apps-r5f-dma-memory@a6000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa6000000 0x00 0x100000>;
		no-map;
	};
	vision_apps_main_r5fss1_core0_memory_region: vision-apps-r5f-memory@a6100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa6100000 0x00 0xf00000>;
		no-map;
	};
	vision_apps_main_r5fss1_core1_dma_memory_region: vision-apps-r5f-dma-memory@a7000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa7000000 0x00 0x100000>;
		no-map;
	};
	vision_apps_main_r5fss1_core1_memory_region: vision-apps-r5f-memory@a7100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa7100000 0x00 0xf00000>;
		no-map;
	};
	vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@a8000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa8000000 0x00 0x100000>;
		no-map;
	};
	vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@a8100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa8100000 0x00 0x1f00000>;
		no-map;
	};
	vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@aa000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xaa000000 0x00 0x100000>;
		no-map;
	};
	vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@aa100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xaa100000 0x00 0x6f00000>;
		no-map;
	};
	vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@b2000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xb2000000 0x00 0x2000000>;
		no-map;
	};
	vision_apps_memory_region: vision-apps-dma-memory@b4000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xb4000000 0x00 0x6000000>;
		no-map;
	};
	vision_apps_shared_region: vision-apps-shared-memories {
		compatible = "dma-heap-carveout";
		reg = <0x00 0xba000000 0x00 0x20000000>;
	};
	vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@da000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xda000000 0x00 0x4000000>;
		no-map;
	};
};

memmap

/* Main OCRAM for MCU2_0 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_0_ADDR (0x03600000u)
#define MAIN_OCRAM_MCU2_0_SIZE (0x00040000u)

/* Main OCRAM for MCU2_1 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_1_ADDR (0x03640000u)
#define MAIN_OCRAM_MCU2_1_SIZE (0x00040000u)

/* L2 for C7x_1 [ size 448.00 KB ] */
#define L2RAM_C7x_1_ADDR (0x64800000u)
#define L2RAM_C7x_1_SIZE (0x00070000u)

/* L1 for C7x_1 [ size 16.00 KB ] */
#define L1RAM_C7x_1_ADDR (0x64E00000u)
#define L1RAM_C7x_1_SIZE (0x00004000u)

/* L2 for C7x_2 [ size 448.00 KB ] */
#define L2RAM_C7x_2_ADDR (0x65800000u)
#define L2RAM_C7x_2_SIZE (0x00070000u)

/* L1 for C7x_2 [ size 16.00 KB ] */
#define L1RAM_C7x_2_ADDR (0x65E00000u)
#define L1RAM_C7x_2_SIZE (0x00004000u)

/* MSMC for C7x_1 [ size  3.78 MB ] */
#define MSMC_C7x_1_ADDR (0x70020000u)
#define MSMC_C7x_1_SIZE (0x003C8000u)

/* DDR for MCU1_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU1_0_IPC_ADDR (0xA0000000u)
#define DDR_MCU1_0_IPC_SIZE (0x00100000u)

/* DDR for MCU1_0 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU1_0_DTS_ADDR (0xA0100000u)
#define DDR_MCU1_0_DTS_SIZE (0x00F00000u)

/* DDR for MCU1_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU1_1_IPC_ADDR (0xA1000000u)
#define DDR_MCU1_1_IPC_SIZE (0x00100000u)

/* DDR for MCU1_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU1_1_DTS_ADDR (0xA1100000u)
#define DDR_MCU1_1_DTS_SIZE (0x00F00000u)

/* DDR for MCU2_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU2_0_IPC_ADDR (0xA2000000u)
#define DDR_MCU2_0_IPC_SIZE (0x00100000u)

/* DDR for MCU2_0 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_MCU2_0_DTS_ADDR (0xA2100000u)
#define DDR_MCU2_0_DTS_SIZE (0x01F00000u)

/* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU2_1_IPC_ADDR (0xA4000000u)
#define DDR_MCU2_1_IPC_SIZE (0x00100000u)

/* DDR for MCU2_1 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_MCU2_1_DTS_ADDR (0xA4100000u)
#define DDR_MCU2_1_DTS_SIZE (0x01F00000u)

/* DDR for MCU3_0 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU3_0_IPC_ADDR (0xA6000000u)
#define DDR_MCU3_0_IPC_SIZE (0x00100000u)

/* DDR for MCU3_0 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU3_0_DTS_ADDR (0xA6100000u)
#define DDR_MCU3_0_DTS_SIZE (0x00F00000u)

/* DDR for MCU3_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_MCU3_1_IPC_ADDR (0xA7000000u)
#define DDR_MCU3_1_IPC_SIZE (0x00100000u)

/* DDR for MCU3_1 for all sections, used for reserving memory in DTS file [ size 15.00 MB ] */
#define DDR_MCU3_1_DTS_ADDR (0xA7100000u)
#define DDR_MCU3_1_DTS_SIZE (0x00F00000u)

/* DDR for C7x_2 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C7x_2_IPC_ADDR (0xA8000000u)
#define DDR_C7x_2_IPC_SIZE (0x00100000u)

/* DDR for C7x_2 for all sections, used for reserving memory in DTS file [ size 31.00 MB ] */
#define DDR_C7x_2_DTS_ADDR (0xA8100000u)
#define DDR_C7x_2_DTS_SIZE (0x01F00000u)

/* DDR for C7x_1 for Linux IPC [ size 1024.00 KB ] */
#define DDR_C7x_1_IPC_ADDR (0xAA000000u)
#define DDR_C7x_1_IPC_SIZE (0x00100000u)

/* DDR for C7x_1 for all sections, used for reserving memory in DTS file [ size 111.00 MB ] */
#define DDR_C7x_1_DTS_ADDR (0xAA100000u)
#define DDR_C7x_1_DTS_SIZE (0x06F00000u)

/* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define IPC_VRING_MEM_ADDR (0xB2000000u)
#define IPC_VRING_MEM_SIZE (0x02000000u)

/* Memory for remote core logging [ size 256.00 KB ] */
#define APP_LOG_MEM_ADDR (0xB4000000u)
#define APP_LOG_MEM_SIZE (0x00040000u)

/* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 55.38 MB ] */
#define TIOVX_OBJ_DESC_MEM_ADDR (0xB4040000u)
#define TIOVX_OBJ_DESC_MEM_SIZE (0x03760000u)

/* Memory for lpc shared memory. MUST be non-cached or cache-coherent [ size  8.00 MB ] */
#define LPC_SHARED_MEM_ADDR (0xB77A0000u)
#define LPC_SHARED_MEM_SIZE (0x00800000u)

/* Memory for global timer memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define GLOBAL_TIMER_MEM_ADDR (0xB7FA0000u)
#define GLOBAL_TIMER_MEM_SIZE (0x00020000u)

/* Memory for vip shared buf memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define VIP_SHARED_BUF_MEM_ADDR (0xB7FC0000u)
#define VIP_SHARED_BUF_MEM_SIZE (0x00020000u)

/* Memory for validate info memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
#define VALIDATE_INFO_MEM_ADDR (0xB7FE0000u)
#define VALIDATE_INFO_MEM_SIZE (0x00020000u)

/* Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
#define TIOVX_LOG_RT_MEM_ADDR (0xB8000000u)
#define TIOVX_LOG_RT_MEM_SIZE (0x02000000u)

/* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
#define DDR_SHARED_MEM_ADDR (0xBA000000u)
#define DDR_SHARED_MEM_SIZE (0x20000000u)

/* DDR for MCU1_0 for local heap [ size  8.00 MB ] */
#define DDR_MCU1_0_LOCAL_HEAP_ADDR (0xDA000000u)
#define DDR_MCU1_0_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU1_1 for local heap [ size  8.00 MB ] */
#define DDR_MCU1_1_LOCAL_HEAP_ADDR (0xDA800000u)
#define DDR_MCU1_1_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU2_0 local heap for tiovx use [ size  8.00 MB ] */
#define DDR_MCU2_0_LOCAL_HEAP_TIOVX_ADDR (0xDB000000u)
#define DDR_MCU2_0_LOCAL_HEAP_TIOVX_SIZE (0x00800000u)

/* DDR for MCU2_0 local heap for normal use [ size  8.00 MB ] */
#define DDR_MCU2_0_LOCAL_HEAP_NORMAL_ADDR (0xDB800000u)
#define DDR_MCU2_0_LOCAL_HEAP_NORMAL_SIZE (0x00800000u)

/* DDR for MCU2_1 local heap for tiovx use [ size  8.00 MB ] */
#define DDR_MCU2_1_LOCAL_HEAP_TIOVX_ADDR (0xDC000000u)
#define DDR_MCU2_1_LOCAL_HEAP_TIOVX_SIZE (0x00800000u)

/* DDR for MCU2_1 local heap for normal use [ size  8.00 MB ] */
#define DDR_MCU2_1_LOCAL_HEAP_NORMAL_ADDR (0xDC800000u)
#define DDR_MCU2_1_LOCAL_HEAP_NORMAL_SIZE (0x00800000u)

/* DDR for MCU3_0 for local heap [ size  8.00 MB ] */
#define DDR_MCU3_0_LOCAL_HEAP_ADDR (0xDD000000u)
#define DDR_MCU3_0_LOCAL_HEAP_SIZE (0x00800000u)

/* DDR for MCU3_1 for local heap [ size  8.00 MB ] */
#define DDR_MCU3_1_LOCAL_HEAP_ADDR (0xDD800000u)
#define DDR_MCU3_1_LOCAL_HEAP_SIZE (0x00800000u)

/* Main OCRAM Physical Address for MCU2_0 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_0_PHYS_ADDR (0x4F02000000u)
#define MAIN_OCRAM_MCU2_0_PHYS_SIZE (0x00040000u)

/* Main OCRAM Physical Address for MCU2_1 [ size 256.00 KB ] */
#define MAIN_OCRAM_MCU2_1_PHYS_ADDR (0x4F02040000u)
#define MAIN_OCRAM_MCU2_1_PHYS_SIZE (0x00040000u)

#define DDR_64BIT_BASE_VADDR (0x100000000u)
#define DDR_64BIT_BASE_PADDR (0x880000000u)

Below are the remoteproc names

root@j721s2-evm:/# head /sys/class/remoteproc/remoteproc*/name
==> /sys/class/remoteproc/remoteproc0/name <==
64800000.dsp

==> /sys/class/remoteproc/remoteproc1/name <==
65800000.dsp

==> /sys/class/remoteproc/remoteproc2/name <==
41000000.r5f

==> /sys/class/remoteproc/remoteproc3/name <==
5c00000.r5f

==> /sys/class/remoteproc/remoteproc4/name <==
5d00000.r5f

Resource table :

root@j721s2-evm:/# cat /sys/kernel/debug/remoteproc/remoteproc*/resource_table
Entry 0 is of type vdev
ID 7
Notify ID 0
Device features 0x1
Guest features 0x1
Config length 0x0
Status 0x7
Number of vrings 2
Reserved (should be zero) [0][0]

Vring 0
Device Address 0xaa000000
Alignment 4096
Number of buffers 256
Notify ID 0
Physical Address 0x0

Vring 1
Device Address 0xaa004000
Alignment 4096
Number of buffers 256
Notify ID 1
Physical Address 0x0

Unknown resource type found: 65538 [hdr: 000000004ef6bb48]
Entry 0 is of type vdev
ID 7
Notify ID 0
Device features 0x1
Guest features 0x1
Config length 0x0
Status 0x7
Number of vrings 2
Reserved (should be zero) [0][0]

Vring 0
Device Address 0xa8000000
Alignment 4096
Number of buffers 256
Notify ID 0
Physical Address 0x0

Vring 1
Device Address 0xa8004000
Alignment 4096
Number of buffers 256
Notify ID 1
Physical Address 0x0

Unknown resource type found: 65538 [hdr: 000000003d080f6e]
Entry 0 is of type vdev
ID 7
Notify ID 0
Device features 0x1
Guest features 0x1
Config length 0x0
Status 0x7
Number of vrings 2
Reserved (should be zero) [0][0]

Vring 0
Device Address 0xa0000000
Alignment 4096
Number of buffers 256
Notify ID 0
Physical Address 0x0

Vring 1
Device Address 0xa0004000
Alignment 4096
Number of buffers 256
Notify ID 1
Physical Address 0x0

Entry 1 is of type trace
Device Address 0xa066a7b0
Length 0x80000 Bytes
Reserved (should be zero) [0]
Name trace:r5f0

Entry 0 is of type vdev
ID 7
Notify ID 0
Device features 0x1
Guest features 0x1
Config length 0x0
Status 0x7
Number of vrings 2
Reserved (should be zero) [0][0]

Vring 0
Device Address 0xa2000000
Alignment 4096
Number of buffers 256
Notify ID 0
Physical Address 0x0

Vring 1
Device Address 0xa2004000
Alignment 4096
Number of buffers 256
Notify ID 1
Physical Address 0x0

Entry 1 is of type trace
Device Address 0xa3c9e800
Length 0x80000 Bytes
Reserved (should be zero) [0]
Name trace:r5f0

Entry 0 is of type vdev
ID 7
Notify ID 0
Device features 0x1
Guest features 0x1
Config length 0x0
Status 0x7
Number of vrings 2
Reserved (should be zero) [0][0]

Vring 0
Device Address 0xa4000000
Alignment 4096
Number of buffers 256
Notify ID 0
Physical Address 0x0

Vring 1
Device Address 0xa4004000
Alignment 4096
Number of buffers 256
Notify ID 1
Physical Address 0x0

Entry 1 is of type trace
Device Address 0xa5470000
Length 0x80000 Bytes
Reserved (should be zero) [0]
Name trace:r5f0

root@j721s2-evm:/# ls -l /sys/dev/char
lrwxrwxrwx 1 root root 0 Jun 16 17:02 10:196 -> ../../devices/virtual/misc/vfio
lrwxrwxrwx 1 root root 0 Jun 16 17:02 10:200 -> ../../devices/virtual/misc/tun
lrwxrwxrwx 1 root root 0 Jun 16 17:02 10:231 -> ../../devices/virtual/misc/snapshot
lrwxrwxrwx 1 root root 0 Jun 16 17:02 10:235 -> ../../devices/virtual/misc/autofs
lrwxrwxrwx 1 root root 0 Jun 16 17:02 10:237 -> ../../devices/virtual/misc/loop-control
lrwxrwxrwx 1 root root 0 Jun 16 17:02 10:61 -> ../../devices/virtual/misc/pvr_sync
lrwxrwxrwx 1 root root 0 Jun 16 17:02 10:62 -> ../../devices/virtual/misc/ubi_ctrl
lrwxrwxrwx 1 root root 0 Jun 16 17:02 10:63 -> ../../devices/platform/dma_buf_phys/misc/dma-buf-phys
lrwxrwxrwx 1 root root 0 Jun 16 17:02 116:33 -> ../../devices/virtual/sound/timer
lrwxrwxrwx 1 root root 0 Jun 16 17:02 1:1 -> ../../devices/virtual/mem/mem
lrwxrwxrwx 1 root root 0 Jun 16 17:02 1:11 -> ../../devices/virtual/mem/kmsg
lrwxrwxrwx 1 root root 0 Jun 16 17:02 1:3 -> ../../devices/virtual/mem/null
lrwxrwxrwx 1 root root 0 Jun 16 17:02 1:4 -> ../../devices/virtual/mem/port
lrwxrwxrwx 1 root root 0 Jun 16 17:02 1:5 -> ../../devices/virtual/mem/zero
lrwxrwxrwx 1 root root 0 Jun 16 17:02 1:7 -> ../../devices/virtual/mem/full
lrwxrwxrwx 1 root root 0 Jun 16 17:02 1:8 -> ../../devices/virtual/mem/random
lrwxrwxrwx 1 root root 0 Jun 16 17:02 1:9 -> ../../devices/virtual/mem/urandom
lrwxrwxrwx 1 root root 0 Jan 1 1970 226:0 -> ../../devices/platform/bus@100000/4e20000000.gpu/drm/card0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 226:128 -> ../../devices/platform/bus@100000/4e20000000.gpu/drm/renderD128
lrwxrwxrwx 1 root root 0 Jun 16 17:02 235:0 -> ../../devices/platform/bus@100000/64800000.dsp/remoteproc/remoteproc0/remoteproc0#vdev0buffer/virtio0/virtio0.rpmsg_chrdev.-1.20/rpmsg/rpmsg_ctrl0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 235:1 -> ../../devices/platform/bus@100000/64800000.dsp/remoteproc/remoteproc0/remoteproc0#vdev0buffer/virtio0/virtio0.rpmsg_chrdev.-1.10/rpmsg/rpmsg_ctrl1
lrwxrwxrwx 1 root root 0 Jun 16 17:02 235:2 -> ../../devices/platform/bus@100000/64800000.dsp/remoteproc/remoteproc0/remoteproc0#vdev0buffer/virtio0/virtio0.rpmsg_chrdev.-1.14/rpmsg/rpmsg_ctrl2
lrwxrwxrwx 1 root root 0 Jun 16 17:02 235:3 -> ../../devices/platform/bus@100000/65800000.dsp/remoteproc/remoteproc1/remoteproc1#vdev0buffer/virtio1/virtio1.rpmsg_chrdev.-1.20/rpmsg/rpmsg_ctrl3
lrwxrwxrwx 1 root root 0 Jun 16 17:02 235:4 -> ../../devices/platform/bus@100000/65800000.dsp/remoteproc/remoteproc1/remoteproc1#vdev0buffer/virtio1/virtio1.rpmsg_chrdev.-1.10/rpmsg/rpmsg_ctrl4
lrwxrwxrwx 1 root root 0 Jun 16 17:02 235:5 -> ../../devices/platform/bus@100000/65800000.dsp/remoteproc/remoteproc1/remoteproc1#vdev0buffer/virtio1/virtio1.rpmsg_chrdev.-1.14/rpmsg/rpmsg_ctrl5
lrwxrwxrwx 1 root root 0 Jun 16 17:02 235:6 -> ../../devices/platform/bus@100000/bus@100000:bus@28380000/bus@100000:bus@28380000:r5fss@41000000/41000000.r5f/remoteproc/remoteproc2/remoteproc2#vdev0buffer/virtio2/virtio2.rpmsg_chrdev.-1.30/rpmsg/rpmsg_ctrl6
lrwxrwxrwx 1 root root 0 Jun 16 17:02 235:7 -> ../../devices/platform/bus@100000/bus@100000:bus@28380000/bus@100000:bus@28380000:r5fss@41000000/41000000.r5f/remoteproc/remoteproc2/remoteproc2#vdev0buffer/virtio2/virtio2.rpmsg_chrdev.-1.14/rpmsg/rpmsg_ctrl7
lrwxrwxrwx 1 root root 0 Jun 16 17:02 236:0 -> ../../devices/virtual/ubi/ubi0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 236:1 -> ../../devices/virtual/ubi/ubi0/ubi0_0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 237:0 -> ../../devices/platform/bus@100000/4f80000.mmc/mmc_host/mmc0/mmc0:0001/mmcblk0rpmb
lrwxrwxrwx 1 root root 0 Jun 16 17:02 245:0 -> ../../devices/virtual/tee/tee0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 245:16 -> ../../devices/virtual/tee/teepriv0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 247:0 -> ../../devices/platform/bus@100000/c200000.ethernet/ptp/ptp0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 247:1 -> ../../devices/platform/bus@100000/bus@100000:bus@30000000/310d0000.cpts/ptp/ptp1
lrwxrwxrwx 1 root root 0 Jun 16 17:02 253:0 -> ../../devices/virtual/dma_heap/vision-apps-shared-memories
lrwxrwxrwx 1 root root 0 Jun 16 17:02 253:1 -> ../../devices/virtual/dma_heap/system
lrwxrwxrwx 1 root root 0 Jun 16 17:02 253:2 -> ../../devices/virtual/dma_heap/reserved
lrwxrwxrwx 1 root root 0 Jun 16 17:02 254:0 -> ../../devices/platform/bus@100000/bus@100000:bus@28380000/42110000.gpio/gpiochip0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 254:1 -> ../../devices/platform/bus@100000/600000.gpio/gpiochip1
lrwxrwxrwx 1 root root 0 Jun 16 17:02 2:0 -> ../../devices/virtual/tty/ptyp0
lrwxrwxrwx 1 root root 0 Jun 16 17:02 2:1 -> ../../devices/virtual/tty/ptyp1
lrwxrwxrwx 1 root root 0 Jun 16 17:02 2:10 -> ../../devices/virtual/tty/ptypa
lrwxrwxrwx 1 root root 0 Jun 16 17:02 2:11 -> ../../devices/virtual/tty/ptypb
lrwxrwxrwx 1 root root 0 Jun 16 17:02 2:12 -> ../../dev

remote proc for device mcu's are not created as per the log.

linker command for r5f0 is

MEMORY
{
    /* R5F_TCMA_VECS [ size 64 B ] */
    R5F_TCMA_VECS            (    X ) : ORIGIN = 0x00000000 , LENGTH = 0x00000040
    /* R5F_TCMA [ size 31.94 KB ] */
    R5F_TCMA                 (    X ) : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
    /* Main OCRAM for MCU2_0 [ size 256.00 KB ] */
    MAIN_OCRAM_MCU2_0        ( RWIX ) : ORIGIN = 0x03600000 , LENGTH = 0x00040000
    /* R5F_TCMB0 [ size 32.00 KB ] */
    R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
    /* DDR for MCU2_0 for Linux IPC [ size 1024.00 KB ] */
    DDR_MCU2_0_IPC           ( RWIX ) : ORIGIN = 0xA2000000 , LENGTH = 0x00100000
    /* DDR for MCU2_0 for Linux resource table [ size 1024 B ] */
    DDR_MCU2_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA2100000 , LENGTH = 0x00000400
    /* DDR for MCU2_0 for code/data [ size 31.00 MB ] */
    DDR_MCU2_0               ( RWIX ) : ORIGIN = 0xA2100400 , LENGTH = 0x01EFFC00
    /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
    IPC_VRING_MEM                     : ORIGIN = 0xB2000000 , LENGTH = 0x02000000
    /* Memory for remote core logging [ size 256.00 KB ] */
    APP_LOG_MEM                       : ORIGIN = 0xB4000000 , LENGTH = 0x00040000
    /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 55.38 MB ] */
    TIOVX_OBJ_DESC_MEM                : ORIGIN = 0xB4040000 , LENGTH = 0x03760000
    /* Memory for lpc shared memory. MUST be non-cached or cache-coherent [ size  8.00 MB ] */
    LPC_SHARED_MEM                    : ORIGIN = 0xB77A0000 , LENGTH = 0x00800000
    /* Memory for global timer memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
    GLOBAL_TIMER_MEM                  : ORIGIN = 0xB7FA0000 , LENGTH = 0x00020000
    /* Memory for vip shared buf memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
    VIP_SHARED_BUF_MEM                : ORIGIN = 0xB7FC0000 , LENGTH = 0x00020000
    /* Memory for validate info memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
    VALIDATE_INFO_MEM                 : ORIGIN = 0xB7FE0000 , LENGTH = 0x00020000
    /* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
    DDR_SHARED_MEM                    : ORIGIN = 0xBA000000 , LENGTH = 0x20000000
    /* DDR for MCU2_0 local heap for tiovx use [ size  8.00 MB ] */
    DDR_MCU2_0_LOCAL_HEAP_TIOVX ( RWIX ) : ORIGIN = 0xDB000000 , LENGTH = 0x00800000
    /* DDR for MCU2_0 local heap for normal use [ size  8.00 MB ] */
    DDR_MCU2_0_LOCAL_HEAP_NORMAL ( RWIX ) : ORIGIN = 0xDB800000 , LENGTH = 0x00800000
}

r5f1

MEMORY
{
    /* R5F_TCMA_VECS [ size 64 B ] */
    R5F_TCMA_VECS            (    X ) : ORIGIN = 0x00000000 , LENGTH = 0x00000040
    /* R5F_TCMA [ size 31.94 KB ] */
    R5F_TCMA                 (    X ) : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
    /* Main OCRAM for MCU2_1 [ size 256.00 KB ] */
    MAIN_OCRAM_MCU2_1        ( RWIX ) : ORIGIN = 0x03640000 , LENGTH = 0x00040000
    /* R5F_TCMB0 [ size 32.00 KB ] */
    R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
    /* DDR for MCU2_1 for Linux IPC [ size 1024.00 KB ] */
    DDR_MCU2_1_IPC           ( RWIX ) : ORIGIN = 0xA4000000 , LENGTH = 0x00100000
    /* DDR for MCU2_1 for Linux resource table [ size 1024 B ] */
    DDR_MCU2_1_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA4100000 , LENGTH = 0x00000400
    /* DDR for MCU2_1 for code/data [ size 31.00 MB ] */
    DDR_MCU2_1               ( RWIX ) : ORIGIN = 0xA4100400 , LENGTH = 0x01EFFC00
    /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
    IPC_VRING_MEM                     : ORIGIN = 0xB2000000 , LENGTH = 0x02000000
    /* Memory for remote core logging [ size 256.00 KB ] */
    APP_LOG_MEM                       : ORIGIN = 0xB4000000 , LENGTH = 0x00040000
    /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 55.38 MB ] */
    TIOVX_OBJ_DESC_MEM                : ORIGIN = 0xB4040000 , LENGTH = 0x03760000
    /* Memory for lpc shared memory. MUST be non-cached or cache-coherent [ size  8.00 MB ] */
    LPC_SHARED_MEM                    : ORIGIN = 0xB77A0000 , LENGTH = 0x00800000
    /* Memory for global timer memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
    GLOBAL_TIMER_MEM                  : ORIGIN = 0xB7FA0000 , LENGTH = 0x00020000
    /* Memory for vip shared buf memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
    VIP_SHARED_BUF_MEM                : ORIGIN = 0xB7FC0000 , LENGTH = 0x00020000
    /* Memory for validate info memory. MUST be non-cached or cache-coherent [ size 128.00 KB ] */
    VALIDATE_INFO_MEM                 : ORIGIN = 0xB7FE0000 , LENGTH = 0x00020000
    /* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
    DDR_SHARED_MEM                    : ORIGIN = 0xBA000000 , LENGTH = 0x20000000
    /* DDR for MCU2_1 local heap for tiovx use [ size  8.00 MB ] */
    DDR_MCU2_1_LOCAL_HEAP_TIOVX ( RWIX ) : ORIGIN = 0xDC000000 , LENGTH = 0x00800000
    /* DDR for MCU2_1 local heap for normal use [ size  8.00 MB ] */
    DDR_MCU2_1_LOCAL_HEAP_NORMAL ( RWIX ) : ORIGIN = 0xDC800000 , LENGTH = 0x00800000
}

I couldn't connect the debugger because i am facing configuration problems. So couldn't debug by loading each image.

k3-j721s2-vision-apps.dtbo (since the complete file is not able attach I just pasted only memory node details)

|/fragment@17/__overlay__/vision-apps-r5f-dma-memory@a0000000          9   «/fragment@17/__overlay__/vision-apps-r5f-memory@a0100000          =   Φ/fragment@17/__overlay__/vision-apps-r5f-dma-memory@a1000000          9  
/fragment@17/__overlay__/vision-apps-r5f-memory@a1100000          =  
0/fragment@17/__overlay__/vision-apps-r5f-dma-memory@a2000000          9  
`/fragment@17/__overlay__/vision-apps-r5f-memory@a2100000          =  
Œ/fragment@17/__overlay__/vision-apps-r5f-dma-memory@a4000000          9  
Ό/fragment@17/__overlay__/vision-apps-r5f-memory@a4100000          =  
θ/fragment@17/__overlay__/vision-apps-r5f-dma-memory@a6000000          9  /fragment@17/__overlay__/vision-apps-r5f-memory@a6100000          =  D/fragment@17/__overlay__/vision-apps-r5f-dma-memory@a7000000          9  t/fragment@17/__overlay__/vision-apps-r5f-memory@a7100000          E   /fragment@17/__overlay__/vision-apps-rtos-ipc-memory-region@a8000000          9  Γ/fragment@17/__overlay__/vision-apps-dma-memory@aa000000          =  έ/fragment@17/__overlay__/vision-apps-c71-dma-memory@b0000000          ;  
/fragment@17/__overlay__/vision-apps-c71_0-memory@b0100000        ?  !/fragment@17/__overlay__/vision-apps-c71_1-dma-memory@b6000000        ;  E/fragment@17/__overlay__/vision-apps-c71_1-memory@b6100000        5  e/fragment@17/__overlay__/vision_apps_shared-memories          B  /fragment@17/__overlay__/vision-apps-core-heap-memory-lo@d8000000         C  ™/fragment@17/__overlay__/vision-apps-core-heap-memory-hi@880000000        5