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DDR2 configuration for C6472 and MT47H128M16HG-3

WILLIAM ZETTLER
Prodigy 200 points

Hi -

We're trying to bring up a board here using 2 of these DDR2 chips (recommended under TI guidelines), and are having problems. Since it's a new board, we can't tell whether there are issues with the board itself or whether our timing values are simply wrong. I'd like to eliminate the latter.

All these values except SDRFC which seemed extra-baffling, and I don't think is the problem are from my reading of the Micron datasheet.

SDCFG: 0x08738A32 (note: it won't read back like this, because for some reason bit 27 for termination won't stay on. An older chip?

SDTIM1: 0x66DB5B49

SDTIM2: 0x017FC725

SDRFC: 0x0000073B (I just left this value the way it was)

The behavior is quite odd. I write to one location, my data shows up 2 words higher in memory. Most of it, anyway. Lower 16-bits seems favored over upper 16-bits, which means one chip is happier than the other. The upper byte of the upper word seems especially unhappy.

Anybody got a working GEL file for this configuration?

 

  • 0
    Prodigy 200 points

    Following up, it appears that the reason I can't set bit 27 of SDCFG is that the C6472 has no ODT (on-die termination), and therefore the ODT selection bits have no effect.

    The more I think about it and look at it, the stock settings in the GEL file should have been close enough to get good memory behavior, and the failure modes for using them should have been limited to things like bad refresh timing and not getting the full memory range (the stock numbers represent 10 bits of columns instead of 11). It really shouldn't result in things like bad byte selection. So we're looking at the board more closely.

  • 0
    Prodigy 200 points

    This issue can be closed. We found a wiring error on our board.