AM625: Regarding emulator reset

Hello Premalatha Royappan

Thank you for the query. 

Premalatha Royappan said:

However, when we checked on eval board with the same XDS110 debugger, the reset is happening.

Help me understand the SK board version and revision you have.

Is there any change between the EVM and custom board with respect to implementation including power supply.

Regards,

Sreenivasa

Hi Sreenivasa,

We used E1 Starter kit(proc114E1 ). The implementation in our design is that the emu reset is connected to an AND gate, similar to eval board.

Only difference is the supply for the AND gate is at 1.8V as the output MPU_PORZ is a 1.8V signal. Below is our schematic.

When we probed the emu reset,we observed that it is going low but MCU_PORZ is not getting low. we tried with multiple options of pull up on emu reset, as we observed with 4.7K pull up ,the low was at 240mV. So we tried to increase it to 10K, 20K,100K. With 100K the voltage low is almost 0V but still, the AND gate is not driving low when emu reset is low.

the AND gate works fine when watchdog reset is asserted low, meaning that MCU_PORZ is asserted low when WDO_MPU_nRESET gets low. However when emu reset is low MPU_PORZ is not getting low.

Please note the Vil of the AND gate is 0.63V. 

Hello Premalatha Royappan

Thank you.

Premalatha Royappan said:

Please note the Vil of the AND gate is 0.63V. 

Please elaborate your input.

There is an isolation resistor and pull up.

Please isolate the inputs and do a check of the AND gate output.

Regards,

Sreenivasa

Hi Sreenivasa,

 The emu reset from emulator when connected to the AND gate( which is powered by 1.8V) is not able to drive MCU_PORZ low when emu reset is low. We want to know why is this? 

When we isolated the series resistor on emu reset and pulled it low the AND gate o/p goes low.

Kindly let us know what cud be the issue 

Hello Premalatha Royappan

Thank you.

Please isolate the emu reset  0R and verify the EMU reset level.

If there is a series resistor i would recommend you to short and test.

The AND gate seems to be working. Is there a termination on the EMU reset?

Regards,

Sreenivasa

Hi Sreenivasa,

We isolated the series resistor and tested the emu reset signal by providing a pull up near the JTAG connector. When we probed the emu reset signal,it is going low when reset command is given. Later when connected to the AND gate , the emu reset signal is goes low as expected(when reset command is given)but the AND gate o/p is not going low.

Hello Premalatha Royappan

Thank you.

Premalatha Royappan said:

Later when connected to the AND gate , the emu reset signal is goes low as expected(when reset command is given)but the AND gate o/p is not going low.

Can you please provide a scope capture of the input and output

Is there a pull on the output of the and gate.

Regards,

Sreenivasa

Hi Sreenivasa,

There is no pull up on the AND gate o/p. i/p signal emu reset ahs pull up of 4.7K.Following is the capture of emu reset signal with 4.7K pull up,

The o/p of the AND gate is a HIGH at 1.8V.

We want to know why a low on emu reset is not identified as low and outputed on the AND gate o/p?

Kindly let us know

Hello Premalatha Royappan

Thank you for the input.

Premalatha Royappan said:

We want to know why a low on emu reset is not identified as low and outputed on the AND gate o/p?

This is a logic gate related query.

What is the voltage level you are measuring a the AND gate input for emu reset. Looks to be around 0.3 V or more.

Please try varying the pullup and test.

Since i am not aware the XDS110 reset output behavior, i would suggest increasing or decreasing the pull and testing.

Regards,

Sreenivasa

Hello Premalatha Royappan

I assume you have been able to resolve since i have not heard from you.

Do you have some updated?

Regards,

Sreenivasa